/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department, The Mach Operating System project at
* Carnegie-Mellon University and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)machdep.c 8.3 (Berkeley) 1/12/94
* from: Utah Hdr: machdep.c 1.63 91/04/24
*/
int comcnfreq = CONSFREQ;
int comcnspeed = CONSPEED;
tcflag_t comcnmode = CONMODE;
bus_addr_t comcnaddr = (bus_addr_t)CONSADDR;
struct rmixl_config rmixl_configuration;
/*
* array of tested firmware versions
* if you find new ones and they work
* please add them
*/
typedef struct rmiclfw_psb_id {
uint64_t psb_version;
rmixlfw_psb_type_t psb_type;
} rmiclfw_psb_id_t;
static rmiclfw_psb_id_t rmiclfw_psb_id[] = {
{ 0x4958d4fb00000056ULL, PSB_TYPE_RMI },
{ 0x4aacdb6a00000056ULL, PSB_TYPE_RMI },
{ 0x4b67d03200000056ULL, PSB_TYPE_RMI },
{ 0x4c17058b00000056ULL, PSB_TYPE_RMI },
{ 0x49a5a8fa00000056ULL, PSB_TYPE_DELL },
{ 0x4b8ead3100000056ULL, PSB_TYPE_DELL },
};
#define RMICLFW_PSB_VERSIONS_LEN \
(sizeof(rmiclfw_psb_id)/sizeof(rmiclfw_psb_id[0]))
/*
* storage for fixed extent used to allocate physical address regions
* because extent(9) start and end values are u_long, they are only
* 32 bits on a 32 bit kernel, which is insuffucuent since XLS physical
* address is 40 bits wide. So the "physaddr" map stores regions
* in units of megabytes.
*/
static u_long rmixl_physaddr_storage[
EXTENT_FIXED_STORAGE_SIZE(32)/sizeof(u_long)
];
/* Maps for VM objects. */
struct vm_map *phys_map = NULL;
/*
* Set up the exception vectors and CPU-specific function
* vectors early on. We need the wbflush() vector set up
* before comcnattach() is called (or at least before the
* first printf() after that is called).
* Also clears the I+D caches.
*
* specify chip-specific EIRR/EIMR based spl functions
*/
#ifdef MULTIPROCESSOR
mips_vector_init(&rmixl_splsw, true);
#else
mips_vector_init(&rmixl_splsw, false);
#endif
/*
* Obtain the cpu frequency
* Compute the number of ticks for hz.
* Compute the delay divisor.
* Double the Hz if this CPU runs at twice the
* external/cp0-count frequency
*/
curcpu()->ci_cpu_freq = rcp->rc_psb_info.cpu_frequency;
curcpu()->ci_cctr_freq = curcpu()->ci_cpu_freq;
curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
curcpu()->ci_divisor_delay =
((curcpu()->ci_cpu_freq + 500000) / 1000000);
if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
curcpu()->ci_cpu_freq *= 2;
/*
* Look at arguments passed to us and compute boothowto.
* - rmixl firmware gives us a 32 bit argv[i], so adapt
* by forcing sign extension in cast to (char *)
*/
boothowto = RB_AUTOBOOT;
for (int i = 1; i < argc; i++) {
for (char *cp = (char *)(intptr_t)argv[i]; *cp; cp++) {
int howto;
/* Ignore superfluous '-', if there is one */
if (*cp == '-')
continue;
/* get maximum RAM address from the VM clusters */
mem_cluster_maxaddr = 0;
for (u_int i=0; i < mem_cluster_cnt; i++) {
u_quad_t tmp = round_page(
mem_clusters[i].start + mem_clusters[i].size);
if (tmp > mem_cluster_maxaddr)
mem_cluster_maxaddr = tmp;
}
DPRINTF(("mem_cluster_maxaddr %#"PRIx64"\n", mem_cluster_maxaddr));
/*
* Load mem_clusters[] into the VM system.
*/
mips_page_physload(MIPS_KSEG0_START, (vaddr_t) kernend,
mem_clusters, mem_cluster_cnt, NULL, 0);
/*
* Initialize error message buffer (at end of core).
*/
mips_init_msgbuf();
pmap_bootstrap();
/*
* Allocate uarea page for lwp0 and set it.
*/
mips_init_lwp0_uarea();
#if defined(DDB)
if (boothowto & RB_KDB)
Debugger();
#endif
/*
* store (cpu#0) curcpu in COP0 OSSCRATCH0
* used in exception vector
*/
__asm __volatile("dmtc0 %0,$%1"
:: "r"(&cpu_info_store), "n"(MIPS_COP_0_OSSCRATCH));
#ifdef MULTIPROCESSOR
mips_fixup_exceptions(rmixl_fixup_cop0_oscratch, NULL);
#endif
rmixl_fixup_curcpu();
}
/*
* set up Processor Control Regs for this core
*/
void
rmixl_pcr_init_core(void)
{
uint32_t r;
#ifdef MULTIPROCESSOR
rmixl_mtcr(RMIXL_PCR_MMU_SETUP, __BITS(2,0));
/* enable MMU clock gating */
/* 4 threads active -- why needed if Global? */
/* enable global TLB mode */
#else
rmixl_mtcr(RMIXL_PCR_THREADEN, 1); /* disable all threads except #0 */
rmixl_mtcr(RMIXL_PCR_MMU_SETUP, 0); /* enable MMU clock gating */
/* set single MMU Thread Mode */
/* TLB is partitioned (1 partition) */
#endif
r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0);
r &= ~__BIT(14); /* disable Unaligned Access */
rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r);
#if defined(DDB) && defined(MIPS_DDB_WATCH)
/*
* clear IEU_DEFEATURE[DBE]
* this enables COP0 watchpoint to trigger T_WATCH exception
* instead of signaling JTAG.
*/
r = rmixl_mfcr(RMIXL_PCR_IEU_DEFEATURE);
r &= ~__BIT(7);
rmixl_mtcr(RMIXL_PCR_IEU_DEFEATURE, r);
#endif
}
/*
* Fixup this direct load cpu_info_store to actually get the current
* CPU's cpu_info from COP0 OSSCRATCH0 and then fix the load to be
* relative from the start of struct cpu_info.
*/
for (uint32_t *insnp = _ftext; insnp < _etext; insnp++) {
const uint32_t insn = *insnp;
if (__predict_false((insn & LOAD_CURCPU_MASK) == LOAD_CURCPU)) {
/*
* Since the register to loaded is located in bits
* 16-20 for the mfc0 and the load instruction we can
* just change the instruction bits around it.
*/
*insnp = insn ^ LOAD_CURCPU ^ MFC0_CURCPU;
mips_icache_sync_range((vaddr_t)insnp, 4);
}
}
}
/*
* ram_seg_resv - cut reserved regions out of segs, fragmenting as needed
*
* we simply build a new table of segs, then copy it back over the given one
* this is inefficient but simple and called only a few times
*
* note: 'last' here means 1st addr past the end of the segment (start+size)
*/
static u_int
ram_seg_resv(phys_ram_seg_t *segs, u_int nsegs,
u_quad_t resv_first, u_quad_t resv_last)
{
u_quad_t first, last;
int new_nsegs=0;
int resv_flag;
phys_ram_seg_t new_segs[VM_PHYSSEG_MAX];
for (u_int i=0; i < nsegs; i++) {
resv_flag = 0;
first = trunc_page(segs[i].start);
last = round_page(segs[i].start + segs[i].size);
/*
* reserved start in segment
* salvage the leading fragment
*/
resv_flag = 1;
new_last = last - (last - resv_first);
KASSERT (new_last > first);
new_segs[new_nsegs].start = first;
new_segs[new_nsegs].size = new_last - first;
new_nsegs++;
}
if ((resv_last > first) && (resv_last < last)) {
u_quad_t new_first;
/*
* reserved end in segment
* salvage the trailing fragment
*/
resv_flag = 1;
new_first = first + (resv_last - first);
KASSERT (last > (new_first + NBPG));
new_segs[new_nsegs].start = new_first;
new_segs[new_nsegs].size = last - new_first;
new_nsegs++;
}
if (resv_flag == 0) {
/*
* nothing reserved here, take it all
*/
new_segs[new_nsegs].start = first;
new_segs[new_nsegs].size = last - first;
new_nsegs++;
}
}
memcpy(segs, new_segs, sizeof(new_segs));
return new_nsegs;
}
/*
* create an extent for physical address space
* these are in units of MB for sake of compression (for sake of 32 bit kernels)
* allocate the regions where we have known functions (DRAM, IO, etc)
* what remains can be allocated as needed for other stuff
* e.g. to configure BARs that are not already initialized and enabled.
*/
static void
rmixl_physaddr_init(void)
{
struct extent *ext;
unsigned long start = 0UL;
unsigned long end = (__BIT(40) / (1024 * 1024)) -1;
u_long base;
u_long size;
uint32_t r;
if (ext == NULL)
panic("%s: extent_create failed", __func__);
/*
* grab regions per DRAM BARs
*/
for (u_int i=0; i < RMIXL_SBC_DRAM_NBARS; i++) {
r = RMIXL_IOREG_READ(RMIXL_SBC_DRAM_BAR(i));
if ((r & RMIXL_DRAM_BAR_STATUS) == 0)
continue; /* not enabled */
base = (u_long)(DRAM_BAR_TO_BASE((uint64_t)r) / (1024 * 1024));
size = (u_long)(DRAM_BAR_TO_SIZE((uint64_t)r) / (1024 * 1024));
/*
* get chip-dependent physaddr regions
*/
switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) {
case CIDFL_RMI_TYPE_XLR:
#if NRMIXL_PCIX
rmixl_physaddr_init_pcix(ext);
#endif
break;
case CIDFL_RMI_TYPE_XLS:
#if NRMIXL_PCIE
rmixl_physaddr_init_pcie(ext);
#endif
break;
case CIDFL_RMI_TYPE_XLP:
/* XXX TBD */
panic("%s: RMI XLP not yet supported", __func__);
}
/*
* at this point all regions left in "physaddr" extent
* are unused holes in the physical address space
* available for use as needed.
*/
rmixl_configuration.rc_phys_ex = ext;
#ifdef MACHDEP_DEBUG
extent_print(ext);
#endif
}
/*
* mem_clusters_init
*
* initialize mem_clusters[] table based on memory address mapping
* provided by boot firmware.
*
* prefer avail_mem_map if we can, otherwise use psb_physaddr_map.
* these will be limited by MEMSIZE if it is configured.
* if neither are available, just use MEMSIZE.
*/
static uint64_t
mem_clusters_init(
rmixlfw_mmap_t *psb_physaddr_map,
rmixlfw_mmap_t *avail_mem_map)
{
rmixlfw_mmap_t *map = NULL;
const char *mapname;
uint64_t sz;
uint64_t sum;
u_int cnt;
#ifdef MEMSIZE
uint64_t memsize = MEMSIZE;
#endif
#ifdef MULTIPROCESSOR
/*
* RMI firmware passes wakeup info structure in CP0 OS Scratch reg #7
* they do not explicitly give us the size of the wakeup area.
* we "know" that firmware loader sets wip->gp thusly:
* gp = stack_start[vcpu] = round_page(wakeup_end) + (vcpu * (PAGE_SIZE * 2))
* so
* round_page(wakeup_end) == gp - (vcpu * (PAGE_SIZE * 2))
* Only the "master" cpu runs this function, so
* vcpu = wip->master_cpu
*/
void
rmixl_get_wakeup_info(struct rmixl_config *rcp)
{
volatile rmixlfw_cpu_wakeup_info_t *wip;
int32_t scratch_7;
intptr_t end;
/*
* Everything related to console initialization is done
* in mach_init().
*/
}
/*
* Allocate memory for variable-sized tables,
*/
void
cpu_startup(void)
{
/*
* Virtual memory is bootstrapped -- notify the bus spaces
* that memory allocation is now safe.
*/
rmixl_configuration.rc_mallocsafe = 1;
/* Do the usual stuff */
cpu_startup_common();
}
int waittime = -1;
void
cpu_reboot(int howto, char *bootstr)
{
/* Take a snapshot before clobbering any registers. */
savectx(lwp_getpcb(curlwp));
if (cold) {
howto |= RB_HALT;
goto haltsys;
}
/* If "always halt" was specified as a boot flag, obey. */
if (boothowto & RB_HALT)
howto |= RB_HALT;
if (howto & RB_HALT) {
printf("\n");
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cnpollc(1); /* For proper keyboard command handling */
cngetc();
cnpollc(0);
}
