/*
* Copyright (c) 1998 by Matthew Jacob
* NASA AMES Research Center.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice immediately at the beginning of the file, without modification,
* this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Taken from:
*
* ``RAWHIDE Systems Programmer's Manual, Revision 1.4''
*/
/*
* WHOAMI Register definitions
*
* The Device ID is an echo of the MID of the CPU reading this register-
* cheezy way to figure out who you are (ask someone else!).
*/
#define MCBUS_CPU_MID(x) ((x) & 0x7)
#define MCBUS_CPU_INFO(x) (((x) >> 6) & 0xff)
#define CPU_Fill_Err 0x80
#define CPU_DTAG_Perr 0x40
#define CPU_RevMask 0x38
#define CPU_RevShift 3
#define CPU_BCacheMask 0x3
#define CPU_BCache_0MB 0
#define CPU_BCache_1MB 1
#define CPU_BCache_2MB 2
#define CPU_BCache_4MB 3
/*
* PCI Latency Register Definitions
*/
#define PCI_LAT_SHIFT 8 /* it's in the 2nd byte. */
/*
* CAP Control Register Definitions
*/
#define CAP_LED_ON 0x00000001 /* Selftest LED passed */
#define CAP_EV56_BW_EN 0x00000002 /* BW Enables (EV56, EV6 only) */
#define CAP_DLY_RD_EN 0x00000010 /* PCI Delayed Reads Enabled */
#define CAP_MEM_EN 0x00000020 /* Respond to PCI transactions */
#define CAP_REQ64_EN 0x00000040 /* Request 64 bit data transactions */
#define CAP_ACK64_EN 0x00000080 /* Respond to 64 bit data "" */
#define CAP_ADR_PAR_EN 0x00000100 /* Check PCI address Parity */
#define CAP_MC_CA_PAR 0x00000200 /* Check MC bus CMD/Address Parity */
#define CAP_MC_NXM_EN 0x00000400 /* Check for MC NXM */
#define CAP_BUS_MON 0x00000800 /* Check for PCI errs (as bystander) */
/* bits 19:16 control number of pending write transactions */
#define SHORT 0
#define MED 1
#define LONG 2
#define CAP_MEMRD_PREFETCH_SHIFT 20
#define CAP_MEMRDLN_PREFETCH_SHIFT 22
#define CAP_MEMRDMULT_PREFETCH_SHIFT 24
#define CAP_PARTIAL_WRITE (1 << 26)
/*
* Diagnostic Register Bits
*/
/* CAP_DIAG register */
#define CAP_DIAG_PCIRESET 0x1 /*
* WriteOnly. Assert 1 for 100usec min.,
* then write zero. NOTE: deadlocks
* exist in h/w if anything but this
* register is accessed while reset
* is asserted.
*/
#define CAP_DIAG_MC_ADRPE (1<<30) /* Invert MC Bus Address/Parity */
#define CAP_DIAG_PCI_ADRPE (1<<31) /* Force bad PCI parity (low 32) */
/* MDPA_DIAG or MDPB_DIAG registers */
#define MDPX_ECC_ENA (1<<28) /* Enable ECC on MC Bus (default 1) */
#define MDPX_PAR_ENA (1<<29) /* Enable Parity on PCI (default 0) */
#define MDPX_DIAG_FPE_PCI (1<<30) /* Force PCI parity error */
#define MDPX_DIAG_USE_CHK (1<<31) /*
* When set, DMA write cycles use the
* value in the low 8 bits of this
* register (MDPA or MDPB) as ECC
* sent onto main memory.
*/
/*
* Interrupt Specific bits...
*
* Mostly we don't have to mess with any of the interrupt specific registers
* as the SRM has set most of this pretty complex stuff up for us.
*
* However, to enable specific interrupts, we need to set some bits
* in imask0 if we want to have them vectored to PALcode for appropriate
* dispatch.
*/
/*
* bits 0-15 correspond to 4 slots (time 4 buspins) for each PCI bus.
* bit 16 is the NCR810 onboard SCSI interrupt.
* bits 19-20 are reserved.
*/
/*
* The WBASEX register contains bits 39:10 of a physical address
* shifted to bits 31:2 of this 32 bit register. Namely, shifted
* right by 8 bits.
*/
#define MCPCIA_TBASEX_SHIFT 8
