Copyright (C) 2003-2024 Free Software Foundation, Inc.
This file is part of GDB, GAS, and GNU binutils.
GDB, GAS and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* The highest architecture in the table. */
#define VISIUM_OPCODE_ARCH_MAX (VISIUM_OPCODE_ARCH_BAD - 1)
/* Given an enum visium_opcode_arch_val, return the bitmask to use in
insn encoding/decoding. */
#define VISIUM_OPCODE_ARCH_MASK(arch) (1 << (arch))
/* Some defines to make life easy. */
#define MASK_DEF VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_DEF)
#define MASK_GR5 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR5)
#define MASK_GR6 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR6)
/* Bit masks of architectures supporting the insn. */
#define def (MASK_DEF | MASK_GR5 | MASK_GR6)
#define gr5 (MASK_GR5 | MASK_GR6)
#define gr6 (MASK_GR6)
/* The condition code field is not used (zero) for most instructions.
BRR and BRA make normal use of it. Floating point instructions use
it as a sub-opcode. */
#define CC_MASK (0xf << 27)
/* It seems a shame not to use these bits in a class 0 instruction,
since they could be used to extend the range of the branch. */
#define CLASS0_UNUSED_MASK (0x1f << 16)
/* For class 1 instructions the following bit is unused. */
#define CLASS1_UNUSED_MASK (1 << 9)
/* For class 1 instructions this field gives the index for a write
instruction, the specific operation for an EAM instruction, or
the floating point destination register for a floating point
instruction. */
#define CLASS1_INDEX_MASK (0x1f << 10)
/* For class 3 instructions the following field gives the destination
general register. */
#define CLASS3_DEST_MASK (0x1f << 10)
/* For class 1 and class 3 instructions the following bit selects an
EAM write/read rather than a memory write/read. */
#define EAM_SELECT_MASK (1 << 15)
/* Floating point instructions are distinguished from general EAM
instructions by the following bit. */
#define FP_SELECT_MASK (1 << 3)
/* For both class 1 and class 3 the following fields give, where
appropriate the srcA and srcB registers whether floating point
or general. */
#define SRCA_MASK (0x1f << 16)
#define SRCB_MASK (0x1f << 4)
/* The class 3 interrupt bit. It turns a BRA into a SYS1, and an
RFLAG into a SYS2. This bit should not be set in the user's
class 3 instructions. This bit is also used in class 3
to distinguish between floating point and other EAM operations.
(see FP_SELECT_MASK). */
#define CLASS3_INT (1 << 3)
/* Class 3 shift instructions use this bit to indicate that the
srcB field is a 5 bit immediate shift count rather than a
register number. */
#define CLASS3_SOURCEB_IMMED (1 << 9)