/* ARM COFF support for BFD.
Copyright (C) 1998-2024 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* Bits for f_flags:
F_RELFLG relocation info stripped from file
F_EXEC file is executable (no unresolved external references)
F_LNNO line numbers stripped from file
F_LSYMS local symbols stripped from file
F_INTERWORK file supports switching between ARM and Thumb instruction sets
F_INTERWORK_SET the F_INTERWORK bit is valid
F_APCS_FLOAT code passes float arguments in float registers
F_PIC code is reentrant/position-independent
F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax)
F_APCS_26 file uses 26 bit ARM Procedure Calling Standard
F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised
F_SOFT_FLOAT code does not use floating point instructions. */
/*
ARMMAGIC ought to encoded the procesor type,
but it is too late to change it now, instead
the flags field of the internal_f structure
is used as shown above.