--- gcc-3.3.4/gcc/config/s390/2064.md.orig 2004-06-23 14:31:36.000000000 -0400
+++ gcc-3.3.4/gcc/config/s390/2064.md 2004-06-23 14:31:36.000000000 -0400
@@ -0,0 +1,131 @@
+;; Scheduling description for z900 (cpu 2064).
+;; Copyright (C) 2003 Free Software Foundation, Inc.
+;; Contributed by Hartmut Penner (
[email protected]) and
+;; Ulrich Weigand (
[email protected]).
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;;
+;; References:
+;; The microarchitecture of the IBM eServer z900 processor.
+;; E.M. Schwarz et al.
+;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
+;;
+;; z900 (cpu 2064) pipeline
+;;
+;; dec
+;; --> | <---
+;; LA bypass | agen |
+;; | | |
+;; --- c1 | Load bypass
+;; | |
+;; c2----
+;; |
+;; e1
+;; |
+;; wr
+
+(define_automaton "z_ipu")
+(define_cpu_unit "z_e1" "z_ipu")
+(define_cpu_unit "z_wr" "z_ipu")
+
+
+(define_insn_reservation "z_la" 1
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "la"))
+ "z_e1,z_wr")
+
+(define_insn_reservation "z_larl" 1
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "larl"))
+ "z_e1,z_wr")
+
+(define_insn_reservation "z_load" 1
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "load"))
+ "z_e1,z_wr")
+
+(define_insn_reservation "z_store" 1
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "store"))
+ "z_e1,z_wr")
+
+(define_insn_reservation "z_call" 5
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "jsr"))
+ "z_e1*5,z_wr")
+
+(define_insn_reservation "z_o2" 2
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "o2"))
+ "z_e1*2,z_wr")
+
+(define_insn_reservation "z_o3" 3
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "type" "o3"))
+ "z_e1*3,z_wr")
+
+;
+; Insn still not mentioned are check for
+; the usage of the agen unit
+;
+
+(define_insn_reservation "z_int" 1
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "atype" "reg"))
+ "z_e1,z_wr")
+
+(define_insn_reservation "z_agen" 1
+ (and (eq_attr "cpu" "z900")
+ (eq_attr "atype" "agen"))
+ "z_e1,z_wr")
+
+
+;;
+;; s390_agen_dep_p returns 1, if a register is set in the
+;; first insn and used in the dependend insn to form a address.
+;;
+
+;;
+;; If a intruction uses a register to address memory, it needs
+;; to be set 5 cycles in advance.
+;;
+
+(define_bypass 5 "z_int,z_agen"
+ "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
+
+;;
+;; A load type instruction uses a bypass to feed the result back
+;; to the address generation pipeline stage.
+;;
+
+(define_bypass 3 "z_load"
+ "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
+
+;;
+;; A load address type instruction uses a bypass to feed the
+;; result back to the address generation pipeline stage.
+;;
+
+(define_bypass 2 "z_larl,z_la"
+ "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
+
+
+
+
+
--- gcc-3.3.4/gcc/config/s390/2084.md.orig 2004-06-23 14:31:36.000000000 -0400
+++ gcc-3.3.4/gcc/config/s390/2084.md 2004-06-23 14:31:36.000000000 -0400
@@ -0,0 +1,262 @@
+;; Scheduling description for z990 (cpu 2084).
+;; Copyright (C) 2003 Free Software Foundation, Inc.
+;; Contributed by Hartmut Penner (
[email protected]) and
+;; Ulrich Weigand (
[email protected]).
+;;
+;; This file is part of GNU CC.
+;;
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+(define_automaton "x_ipu")
+
+(define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu")
+(define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
+(define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu")
+(define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu")
+(define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu")
+(define_cpu_unit "x_store_tok" "x_ipu")
+(define_cpu_unit "x_ms,x_mt" "x_ipu")
+
+(define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
+
+(define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
+
+(absence_set "x_e1_r" "x_e1_s,x_e1_t")
+(absence_set "x_e1_s" "x_e1_t")
+
+;; Try to avoid int <-> fp transitions.
+
+(define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
+(define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
+(define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
+(define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
+(define_reservation "x-wr-fp" "x_wr_fp,x-f")
+(define_reservation "x-mem" "x_ms|x_mt")
+
+(absence_set "x_wr_fp"
+ "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
+
+(absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
+ "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
+
+;; Don't have any load type insn in same group as store
+
+(absence_set "x_ms,x_mt" "x_store_tok")
+
+
+;;
+;; Simple insns
+;;
+
+(define_insn_reservation "x_lr" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "lr"))
+ "x-e1-st,x-wr-st")
+
+(define_insn_reservation "x_la" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "la"))
+ "x-e1-st,x-wr-st")
+
+(define_insn_reservation "x_larl" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "larl"))
+ "x-e1-st,x-wr-st")
+
+(define_insn_reservation "x_load" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "load"))
+ "x-e1-st+x-mem,x-wr-st")
+
+(define_insn_reservation "x_store" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "store"))
+ "x-e1-st+x_store_tok,x-wr-st")
+
+(define_insn_reservation "x_branch" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "branch"))
+ "x_e1_r,x_wr_r")
+
+(define_insn_reservation "x_call" 5
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "jsr"))
+ "x-e1-np*5,x-wr-np")
+
+;;
+;; Multicycle insns
+;;
+
+(define_insn_reservation "x_ss" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "op_type" "SS"))
+ "x-e1-np,x-wr-np")
+
+(define_insn_reservation "x_stm" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "stm"))
+ "(x-e1-np+x_store_tok)*10,x-wr-np")
+
+(define_insn_reservation "x_lm" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "lm"))
+ "x-e1-np*10,x-wr-np")
+
+(define_insn_reservation "x_nn" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "op_type" "NN"))
+ "x-e1-np,x-wr-np")
+
+(define_insn_reservation "x_o2" 2
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "o2"))
+ "x-e1-np*2,x-wr-np")
+
+(define_insn_reservation "x_o3" 3
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "o3"))
+ "x-e1-np*3,x-wr-np")
+
+;;
+;; Floating point insns
+;;
+
+(define_insn_reservation "x_fsimpd" 6
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "fsimpd,fmuld"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_fsimps" 6
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "fsimps,fmuls"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_fdivd" 36
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "fdivd"))
+ "x_e1_t*30,x-wr-fp")
+
+(define_insn_reservation "x_fdivs" 36
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "fdivs"))
+ "x_e1_t*30,x-wr-fp")
+
+(define_insn_reservation "x_floadd" 6
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "floadd"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_floads" 6
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "floads"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_fstored" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "fstored"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_fstores" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "fstores"))
+ "x_e1_t,x-wr-fp")
+
+(define_insn_reservation "x_ftoi" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "ftoi"))
+ "x_e1_t*3,x-wr-fp")
+
+(define_insn_reservation "x_itof" 7
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "type" "itof"))
+ "x_e1_t*3,x-wr-fp")
+
+(define_bypass 1 "x_fsimpd" "x_fstored")
+
+(define_bypass 1 "x_fsimps" "x_fstores")
+
+(define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd")
+
+(define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads")
+
+;;
+;; Insns still not mentioned are checked for
+;; the usage of the agen unit
+;;
+
+(define_insn_reservation "x_int" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "atype" "reg"))
+ "x-e1-st,x-wr-st")
+
+(define_insn_reservation "x_agen" 1
+ (and (eq_attr "cpu" "z990")
+ (eq_attr "atype" "agen"))
+ "x-e1-st+x-mem,x-wr-st")
+
+;;
+;; s390_agen_dep_p returns 1, if a register is set in the
+;; first insn and used in the dependend insn to form a address.
+;;
+
+;;
+;; If a intruction uses a register to address memory, it needs
+;; to be set 5 cycles in advance.
+;;
+
+(define_bypass 5 "x_int,x_agen,x_lr"
+ "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
+ "s390_agen_dep_p")
+
+(define_bypass 9 "x_int,x_agen,x_lr"
+ "x_floadd, x_floads, x_fstored, x_fstores,\
+ x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
+ "s390_agen_dep_p")
+;;
+;; A load type instruction uses a bypass to feed the result back
+;; to the address generation pipeline stage.
+;;
+
+(define_bypass 4 "x_load"
+ "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
+ "s390_agen_dep_p")
+
+(define_bypass 5 "x_load"
+ "x_floadd, x_floads, x_fstored, x_fstores,\
+ x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
+ "s390_agen_dep_p")
+
+;;
+;; A load address type instruction uses a bypass to feed the
+;; result back to the address generation pipeline stage.
+;;
+
+(define_bypass 3 "x_larl,x_la"
+ "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
+ "s390_agen_dep_p")
+
+(define_bypass 5 "x_larl, x_la"
+ "x_floadd, x_floads, x_fstored, x_fstores,\
+ x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
+ "s390_agen_dep_p")
+
+;;
+;; Operand forwarding
+;;
+
+(define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
+
+
--- gcc-3.3.4/gcc/config/s390/linux.h.orig 2003-11-14 01:46:10.000000000 -0500
+++ gcc-3.3.4/gcc/config/s390/linux.h 2004-06-23 14:31:36.000000000 -0400
@@ -70,14 +70,34 @@
/* Target specific assembler settings. */
+/* ??? This reimplements the default rules from override_options.
+ There should be a better way to do this. */
+
#ifdef DEFAULT_TARGET_64BIT
-#undef ASM_SPEC
-#define ASM_SPEC "%{m31:-m31 -Aesa}"
+#define ASM_DEFAULT_ABI_SPEC "-m64"
+#define ASM_DEFAULT_MODE_SPEC "%{m31:-mesa}%{m64:-mzarch}\
+%{!m31:%{!m64:-mzarch}}"
+#define ASM_DEFAULT_ARCH_SPEC "%{mesa:g5}%{mzarch:z900}\
+%{!mesa:%{!mzarch:%{m31:g5}%{m64:z900}%{!m31:%{!m64:z900}}}}"
#else
-#undef ASM_SPEC
-#define ASM_SPEC "%{m64:-m64 -Aesame}"
+#define ASM_DEFAULT_ABI_SPEC "-m31"
+#define ASM_DEFAULT_MODE_SPEC "%{m31:-mesa}%{m64:-mzarch}\
+%{!m31:%{!m64:-mesa}}"
+#define ASM_DEFAULT_ARCH_SPEC "%{mesa:g5}%{mzarch:z900}\
+%{!mesa:%{!mzarch:%{m31:g5}%{m64:z900}%{!m31:%{!m64:g5}}}}"
#endif
+#ifdef TARGET_CPU_DEFAULT
+#undef ASM_DEFAULT_ARCH_SPEC
+#define ASM_DEFAULT_ARCH_SPEC TARGET_CPU_DEFAULT
+#endif
+
+#undef ASM_SPEC
+#define ASM_SPEC "\
+%{m31:-m31}%{m64:-m64}%{!m31:%{!m64:%(asm_default_abi)}} \
+%{mesa:-mesa}%{mzarch:-mzarch}%{!mesa:%{!mzarch:%(asm_default_mode)}} \
+%{march=*:-march=%*}%{!march=*:-march=%(asm_default_arch)}"
+
/* Target specific linker settings. */
@@ -119,8 +139,11 @@
is an initializer with a subgrouping for each command option. */
#define EXTRA_SPECS \
- { "link_arch31", LINK_ARCH31_SPEC }, \
- { "link_arch64", LINK_ARCH64_SPEC }, \
+ { "asm_default_abi", ASM_DEFAULT_ABI_SPEC }, \
+ { "asm_default_mode", ASM_DEFAULT_MODE_SPEC }, \
+ { "asm_default_arch", ASM_DEFAULT_ARCH_SPEC }, \
+ { "link_arch31", LINK_ARCH31_SPEC }, \
+ { "link_arch64", LINK_ARCH64_SPEC }, \
#define ASM_FILE_END(FILE) \
do { \
--- gcc-3.3.4/gcc/config/s390/s390-protos.h.orig 2003-11-06 16:53:06.000000000 -0500
+++ gcc-3.3.4/gcc/config/s390/s390-protos.h 2004-06-23 14:31:36.000000000 -0400
@@ -30,7 +30,7 @@
#ifdef RTX_CODE
extern int s390_address_cost PARAMS ((rtx));
-extern int q_constraint PARAMS ((rtx));
+extern int s390_extra_constraint PARAMS ((rtx, int));
extern int const0_operand PARAMS ((rtx, enum machine_mode));
extern int consttable_operand PARAMS ((rtx, enum machine_mode));
extern int larl_operand PARAMS ((rtx, enum machine_mode));
@@ -82,6 +82,8 @@
extern void s390_output_dwarf_dtprel PARAMS ((FILE *, int, rtx));
extern rtx s390_simplify_dwarf_addr PARAMS ((rtx));
extern void s390_machine_dependent_reorg PARAMS ((rtx));
+extern int s390_agen_dep_p PARAMS ((rtx, rtx));
+
#endif /* RTX_CODE */
#ifdef TREE_CODE
--- gcc-3.3.4/gcc/config/s390/s390.c.orig 2004-03-13 06:26:34.000000000 -0500
+++ gcc-3.3.4/gcc/config/s390/s390.c 2004-06-23 14:31:36.000000000 -0400
@@ -49,8 +49,6 @@
#include "optabs.h"
static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int));
-static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int s390_adjust_priority PARAMS ((rtx, int));
static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT));
static void s390_encode_section_info PARAMS ((tree, int));
@@ -61,7 +59,14 @@
enum machine_mode, int));
static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree));
+static enum attr_type s390_safe_attr_type PARAMS ((rtx));
+static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int));
+static int s390_adjust_priority PARAMS ((rtx, int));
+static int s390_issue_rate PARAMS ((void));
+static int s390_use_dfa_pipeline_interface PARAMS ((void));
+static int s390_first_cycle_multipass_dfa_lookahead PARAMS ((void));
+static int s390_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
#undef TARGET_ASM_ALIGNED_DI_OP
@@ -78,12 +83,6 @@
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION s390_select_rtx_section
-#undef TARGET_SCHED_ADJUST_COST
-#define TARGET_SCHED_ADJUST_COST s390_adjust_cost
-
-#undef TARGET_SCHED_ADJUST_PRIORITY
-#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
-
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
#undef TARGET_STRIP_NAME_ENCODING
@@ -106,6 +105,19 @@
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST s390_adjust_cost
+#undef TARGET_SCHED_ADJUST_PRIORITY
+#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE s390_use_dfa_pipeline_interface
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
+#undef TARGET_SCHED_REORDER2
+#define TARGET_SCHED_REORDER2 s390_sched_reorder2
+
struct gcc_target targetm = TARGET_INITIALIZER;
extern int reload_completed;
@@ -137,6 +149,17 @@
int pointer;
};
+/* Which cpu are we tuning for. */
+enum processor_type s390_tune;
+enum processor_flags s390_tune_flags;
+/* Which instruction set architecture to use. */
+enum processor_type s390_arch;
+enum processor_flags s390_arch_flags;
+
+/* Strings to hold which cpu and instruction set architecture to use. */
+const char *s390_tune_string; /* for -mtune=<xxx> */
+const char *s390_arch_string; /* for -march=<xxx> */
+
/* Define the structure for the machine field in struct function. */
struct machine_function GTY(())
@@ -164,6 +187,7 @@
static const char *s390_branch_condition_mnemonic PARAMS ((rtx, int));
static int check_mode PARAMS ((rtx, enum machine_mode *));
static int general_s_operand PARAMS ((rtx, enum machine_mode, int));
+static int s390_short_displacement PARAMS ((rtx));
static int s390_decompose_address PARAMS ((rtx, struct s390_address *));
static rtx get_thread_pointer PARAMS ((void));
static rtx legitimize_tls_address PARAMS ((rtx, rtx));
@@ -187,6 +211,11 @@
static rtx restore_gprs PARAMS ((rtx, int, int, int));
static int s390_function_arg_size PARAMS ((enum machine_mode, tree));
static struct machine_function * s390_init_machine_status PARAMS ((void));
+
+/* Check whether integer displacement is in range. */
+#define DISP_IN_RANGE(d) \
+ (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
+ : ((d) >= 0 && (d) <= 4095))
/* Return true if SET either doesn't set the CC register, or else
the source and destination have matching CC modes and that
@@ -895,11 +924,81 @@
void
override_options ()
{
+ int i;
+ static struct pta
+ {
+ const char *const name; /* processor name or nickname. */
+ const enum processor_type processor;
+ const enum processor_flags flags;
+ }
+ const processor_alias_table[] =
+ {
+ {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
+ {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
+ {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
+ {"z990", PROCESSOR_2084, PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT},
+ };
+
+ int const pta_size = ARRAY_SIZE (processor_alias_table);
+
/* Acquire a unique set number for our register saves and restores. */
s390_sr_alias_set = new_alias_set ();
/* Set up function hooks. */
init_machine_status = s390_init_machine_status;
+
+ /* Architecture mode defaults according to ABI. */
+ if (!(target_flags_explicit & MASK_ZARCH))
+ {
+ if (TARGET_64BIT)
+ target_flags |= MASK_ZARCH;
+ else
+ target_flags &= ~MASK_ZARCH;
+ }
+
+ /* Determine processor architectural level. */
+ if (!s390_arch_string)
+#ifdef TARGET_CPU_DEFAULT
+ s390_arch_string = TARGET_CPU_DEFAULT;
+#else
+ s390_arch_string = TARGET_ZARCH? "z900" : "g5";
+#endif
+
+ for (i = 0; i < pta_size; i++)
+ if (! strcmp (s390_arch_string, processor_alias_table[i].name))
+ {
+ s390_arch = processor_alias_table[i].processor;
+ s390_arch_flags = processor_alias_table[i].flags;
+ break;
+ }
+ if (i == pta_size)
+ error ("bad value (%s) for -march= switch", s390_arch_string);
+
+ /* Determine processor to tune for. */
+ if (!s390_tune_string)
+ {
+ s390_tune = s390_arch;
+ s390_tune_flags = s390_arch_flags;
+ s390_tune_string = s390_arch_string;
+ }
+ else
+ {
+ for (i = 0; i < pta_size; i++)
+ if (! strcmp (s390_tune_string, processor_alias_table[i].name))
+ {
+ s390_tune = processor_alias_table[i].processor;
+ s390_tune_flags = processor_alias_table[i].flags;
+ break;
+ }
+ if (i == pta_size)
+ error ("bad value (%s) for -mtune= switch", s390_tune_string);
+ }
+
+ /* Sanity checks. */
+ if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
+ error ("z/Architecture mode not supported on %s", s390_arch_string);
+ if (TARGET_64BIT && !TARGET_ZARCH)
+ error ("64-bit ABI not supported in ESA/390 mode");
}
/* Map for smallest class containing reg regno. */
@@ -916,6 +1015,17 @@
ADDR_REGS, NO_REGS, ADDR_REGS
};
+/* Return attribute type of insn. */
+
+static enum attr_type
+s390_safe_attr_type (insn)
+ rtx insn;
+{
+ if (recog_memoized (insn) >= 0)
+ return get_attr_type (insn);
+ else
+ return TYPE_NONE;
+}
/* Return true if OP a (const_int 0) operand.
OP is the current operation.
@@ -986,12 +1096,17 @@
return 0;
op = XEXP (op, 0);
- /* Allow adding *even* constants. */
+ /* Allow adding *even* in-range constants. */
if (GET_CODE (op) == PLUS)
{
if (GET_CODE (XEXP (op, 1)) != CONST_INT
|| (INTVAL (XEXP (op, 1)) & 1) != 0)
return 0;
+#if HOST_BITS_PER_WIDE_INT > 32
+ if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
+ || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
+ return 0;
+#endif
op = XEXP (op, 0);
}
@@ -1106,24 +1221,121 @@
return general_s_operand (op, mode, 1);
}
-/* Return true if OP is a valid operand for a 'Q' constraint.
- This differs from s_operand in that only memory operands
- without index register are accepted, nothing else. */
+/* Return true if DISP is a valid short displacement. */
+
+static int
+s390_short_displacement (disp)
+ rtx disp;
+{
+ /* No displacement is OK. */
+ if (!disp)
+ return 1;
+
+ /* Integer displacement in range. */
+ if (GET_CODE (disp) == CONST_INT)
+ return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
+
+ /* GOT offset is not OK, the GOT can be large. */
+ if (GET_CODE (disp) == CONST
+ && GET_CODE (XEXP (disp, 0)) == UNSPEC
+ && XINT (XEXP (disp, 0), 1) == 110)
+ return 0;
+
+ /* All other symbolic constants are literal pool references,
+ which are OK as the literal pool must be small. */
+ if (GET_CODE (disp) == CONST)
+ return 1;
+
+ return 0;
+}
+
+/* Return true if OP is a valid operand for a C constraint. */
int
-q_constraint (op)
- register rtx op;
+s390_extra_constraint (op, c)
+ rtx op;
+ int c;
{
struct s390_address addr;
- if (GET_CODE (op) != MEM)
- return 0;
+ switch (c)
+ {
+ case 'Q':
+ if (GET_CODE (op) != MEM)
+ return 0;
+ if (!s390_decompose_address (XEXP (op, 0), &addr))
+ return 0;
+ if (addr.indx)
+ return 0;
- if (!s390_decompose_address (XEXP (op, 0), &addr))
- return 0;
+ if (TARGET_LONG_DISPLACEMENT)
+ {
+ if (!s390_short_displacement (addr.disp))
+ return 0;
+ }
+ break;
- if (addr.indx)
- return 0;
+ case 'R':
+ if (GET_CODE (op) != MEM)
+ return 0;
+
+ if (TARGET_LONG_DISPLACEMENT)
+ {
+ if (!s390_decompose_address (XEXP (op, 0), &addr))
+ return 0;
+ if (!s390_short_displacement (addr.disp))
+ return 0;
+ }
+ break;
+
+ case 'S':
+ if (!TARGET_LONG_DISPLACEMENT)
+ return 0;
+ if (GET_CODE (op) != MEM)
+ return 0;
+ if (!s390_decompose_address (XEXP (op, 0), &addr))
+ return 0;
+ if (addr.indx)
+ return 0;
+ if (s390_short_displacement (addr.disp))
+ return 0;
+ break;
+
+ case 'T':
+ if (!TARGET_LONG_DISPLACEMENT)
+ return 0;
+ if (GET_CODE (op) != MEM)
+ return 0;
+ /* Any invalid address here will be fixed up by reload,
+ so accept it for the most generic constraint. */
+ if (s390_decompose_address (XEXP (op, 0), &addr)
+ && s390_short_displacement (addr.disp))
+ return 0;
+ break;
+
+ case 'U':
+ if (TARGET_LONG_DISPLACEMENT)
+ {
+ if (!s390_decompose_address (op, &addr))
+ return 0;
+ if (!s390_short_displacement (addr.disp))
+ return 0;
+ }
+ break;
+
+ case 'W':
+ if (!TARGET_LONG_DISPLACEMENT)
+ return 0;
+ /* Any invalid address here will be fixed up by reload,
+ so accept it for the most generic constraint. */
+ if (s390_decompose_address (op, &addr)
+ && s390_short_displacement (addr.disp))
+ return 0;
+ break;
+
+ default:
+ return 0;
+ }
return 1;
}
@@ -1491,6 +1703,11 @@
legitimate_reload_constant_p (op)
register rtx op;
{
+ /* Accept la(y) operands. */
+ if (GET_CODE (op) == CONST_INT
+ && DISP_IN_RANGE (INTVAL (op)))
+ return 1;
+
/* Accept l(g)hi operands. */
if (GET_CODE (op) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
@@ -1834,7 +2051,7 @@
this is fixed up by reload in any case. */
if (base != arg_pointer_rtx && indx != arg_pointer_rtx)
{
- if (INTVAL (disp) < 0 || INTVAL (disp) >= 4096)
+ if (!DISP_IN_RANGE (INTVAL (disp)))
return FALSE;
}
}
@@ -2217,7 +2434,7 @@
pair of LARL and LA. */
rtx temp = reg? reg : gen_reg_rtx (Pmode);
- if (INTVAL (op1) < 0 || INTVAL (op1) >= 4096)
+ if (!DISP_IN_RANGE (INTVAL (op1)))
{
int even = INTVAL (op1) - 1;
op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
@@ -2587,8 +2804,8 @@
change later anyway. */
if (GET_CODE (constant_term) == CONST_INT
- && (INTVAL (constant_term) < 0
- || INTVAL (constant_term) >= 4096)
+ && !TARGET_LONG_DISPLACEMENT
+ && !DISP_IN_RANGE (INTVAL (constant_term))
&& !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
{
HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
@@ -3363,9 +3580,6 @@
return default_assemble_integer (x, size, aligned_p);
}
-
-#define DEBUG_SCHED 0
-
/* Returns true if register REGNO is used for forming
a memory address in expression X. */
@@ -3417,6 +3631,9 @@
{
rtx target, pat;
+ if (GET_CODE (dep_rtx) == INSN)
+ dep_rtx = PATTERN (dep_rtx);
+
if (GET_CODE (dep_rtx) == SET)
{
target = SET_DEST (dep_rtx);
@@ -3429,7 +3646,7 @@
{
int regno = REGNO (target);
- if (get_attr_type (insn) == TYPE_LA)
+ if (s390_safe_attr_type (insn) == TYPE_LA)
{
pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL)
@@ -3443,13 +3660,36 @@
else
abort();
}
- else if (get_attr_atype (insn) == ATYPE_MEM)
+ else if (get_attr_atype (insn) == ATYPE_AGEN)
return reg_used_in_mem_p (regno, PATTERN (insn));
}
}
return 0;
}
+/* Return 1, if dep_insn sets register used in insn in the agen unit. */
+
+int
+s390_agen_dep_p(dep_insn, insn)
+ rtx dep_insn;
+ rtx insn;
+{
+ rtx dep_rtx = PATTERN (dep_insn);
+ int i;
+
+ if (GET_CODE (dep_rtx) == SET
+ && addr_generation_dependency_p (dep_rtx, insn))
+ return 1;
+ else if (GET_CODE (dep_rtx) == PARALLEL)
+ {
+ for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
+ {
+ if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
+ return 1;
+ }
+ }
+ return 0;
+}
/* Return the modified cost of the dependency of instruction INSN
on instruction DEP_INSN through the link LINK. COST is the
@@ -3483,52 +3723,42 @@
if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
return cost;
+ /* DFA based scheduling checks address dependency in md file. */
+ if (s390_use_dfa_pipeline_interface ())
+ {
+ /* Operand forward in case of lr, load and la. */
+ if (s390_tune == PROCESSOR_2084
+ && cost == 1
+ && (s390_safe_attr_type (dep_insn) == TYPE_LA
+ || s390_safe_attr_type (dep_insn) == TYPE_LR
+ || s390_safe_attr_type (dep_insn) == TYPE_LOAD))
+ return 0;
+ return cost;
+ }
+
dep_rtx = PATTERN (dep_insn);
- if (GET_CODE (dep_rtx) == SET)
- {
- if (addr_generation_dependency_p (dep_rtx, insn))
- {
- cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
- if (DEBUG_SCHED)
- {
- fprintf (stderr, "\n\nAddress dependency detected: cost %d\n",
- cost);
- debug_rtx (dep_insn);
- debug_rtx (insn);
- }
- }
- }
+ if (GET_CODE (dep_rtx) == SET
+ && addr_generation_dependency_p (dep_rtx, insn))
+ cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
else if (GET_CODE (dep_rtx) == PARALLEL)
{
for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
{
- if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i),
- insn))
- {
- cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
- if (DEBUG_SCHED)
- {
- fprintf (stderr, "\n\nAddress dependency detected: cost %d\n"
- ,cost);
- debug_rtx (dep_insn);
- debug_rtx (insn);
- }
- }
+ if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
+ cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
}
}
return cost;
}
-
-
/* A C statement (sans semicolon) to update the integer scheduling priority
- INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier,
- increase the priority to execute INSN later. Do not define this macro if
+ INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
+ reduce the priority to execute INSN later. Do not define this macro if
you do not need to adjust the scheduling priorities of insns.
- A LA instruction maybe scheduled later, since the pipeline bypasses the
- calculated value. */
+ A STD instruction should be scheduled earlier,
+ in order to use the bypass. */
static int
s390_adjust_priority (insn, priority)
@@ -3538,32 +3768,67 @@
if (! INSN_P (insn))
return priority;
- if (GET_CODE (PATTERN (insn)) == USE
- || GET_CODE (PATTERN (insn)) == CLOBBER)
+ if (s390_tune != PROCESSOR_2084)
return priority;
-
- switch (get_attr_type (insn))
+
+ switch (s390_safe_attr_type (insn))
{
- default:
- break;
-
- case TYPE_LA:
- if (priority >= 0 && priority < 0x01000000)
- priority <<= 3;
- break;
- case TYPE_LM:
- /* LM in epilogue should never be scheduled. This
- is due to literal access done in function body.
- The usage of register 13 is not mentioned explicitly,
- leading to scheduling 'LM' accross this instructions.
- */
- priority = 0x7fffffff;
- break;
+ case TYPE_FSTORED:
+ case TYPE_FSTORES:
+ priority = priority << 3;
+ break;
+ case TYPE_STORE:
+ priority = priority << 1;
+ break;
+ default:
+ break;
}
-
return priority;
}
+/* The number of instructions that can be issued per cycle. */
+
+static int
+s390_issue_rate ()
+{
+ if (s390_tune == PROCESSOR_2084)
+ return 3;
+ return 1;
+}
+
+/* If the following function returns TRUE, we will use the the DFA
+ insn scheduler. */
+
+static int
+s390_use_dfa_pipeline_interface ()
+{
+ if (s390_tune == PROCESSOR_2064_Z900
+ || s390_tune == PROCESSOR_2084)
+ return 1;
+
+ return 0;
+}
+
+static int
+s390_first_cycle_multipass_dfa_lookahead ()
+{
+ return s390_use_dfa_pipeline_interface () ? 4 : 0;
+}
+
+/* Called after issuing each insn.
+ Triggers default sort algorithm to better slot instructions. */
+
+static int
+s390_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
+ FILE *dump ATTRIBUTE_UNUSED;
+ int sched_verbose ATTRIBUTE_UNUSED;
+ rtx *ready ATTRIBUTE_UNUSED;
+ int *pn_ready ATTRIBUTE_UNUSED;
+ int clock_var ATTRIBUTE_UNUSED;
+{
+ return s390_issue_rate();
+}
+
/* Split all branches that exceed the maximum distance.
Returns true if this created a new literal pool entry.
@@ -4832,7 +5097,7 @@
reg = stack_pointer_rtx;
off = GEN_INT (cfun->machine->frame_size + REGNO (return_reg) * UNITS_PER_WORD);
- if (INTVAL (off) >= 4096)
+ if (!DISP_IN_RANGE (INTVAL (off)))
{
off = force_const_mem (Pmode, off);
new_insn = gen_rtx_SET (Pmode, return_reg, off);
@@ -5317,11 +5582,21 @@
/* Substract frame size from stack pointer. */
- frame_off = GEN_INT (-cfun->machine->frame_size);
- if (!CONST_OK_FOR_LETTER_P (-cfun->machine->frame_size, 'K'))
- frame_off = force_const_mem (Pmode, frame_off);
+ if (DISP_IN_RANGE (INTVAL (frame_off)))
+ {
+ insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
+ gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+ frame_off));
+ insn = emit_insn (insn);
+ }
+ else
+ {
+ if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
+ frame_off = force_const_mem (Pmode, frame_off);
+
+ insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
+ }
- insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
@@ -5480,8 +5755,8 @@
{
/* Nothing to restore. */
}
- else if (cfun->machine->frame_size + area_bottom >= 0
- && cfun->machine->frame_size + area_top <= 4096)
+ else if (DISP_IN_RANGE (cfun->machine->frame_size + area_bottom)
+ && DISP_IN_RANGE (cfun->machine->frame_size + area_top-1))
{
/* Area is in range. */
offset = cfun->machine->frame_size;
@@ -5493,10 +5768,19 @@
offset = area_bottom < 0 ? -area_bottom : 0;
frame_off = GEN_INT (cfun->machine->frame_size - offset);
- if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
- frame_off = force_const_mem (Pmode, frame_off);
+ if (DISP_IN_RANGE (INTVAL (frame_off)))
+ {
+ insn = gen_rtx_SET (VOIDmode, frame_pointer,
+ gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
+ insn = emit_insn (insn);
+ }
+ else
+ {
+ if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
+ frame_off = force_const_mem (Pmode, frame_off);
- insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
+ insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
+ }
}
/* Restore call saved fprs. */
@@ -6477,8 +6761,10 @@
if (TARGET_64BIT)
{
/* Setup literal pool pointer if required. */
- if (!CONST_OK_FOR_LETTER_P (delta, 'K')
- || !CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
+ if ((!DISP_IN_RANGE (delta)
+ && !CONST_OK_FOR_LETTER_P (delta, 'K'))
+ || (!DISP_IN_RANGE (vcall_offset)
+ && !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{
op[5] = gen_label_rtx ();
output_asm_insn ("larl\t%4,%5", op);
@@ -6489,6 +6775,8 @@
{
if (CONST_OK_FOR_LETTER_P (delta, 'J'))
output_asm_insn ("la\t%1,%2(%1)", op);
+ else if (DISP_IN_RANGE (delta))
+ output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_LETTER_P (delta, 'K'))
output_asm_insn ("aghi\t%1,%2", op);
else
@@ -6501,7 +6789,7 @@
/* Perform vcall adjustment. */
if (vcall_offset)
{
- if (CONST_OK_FOR_LETTER_P (vcall_offset, 'J'))
+ if (DISP_IN_RANGE (vcall_offset))
{
output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("ag\t%1,%3(%4)", op);
@@ -6545,8 +6833,10 @@
{
/* Setup base pointer if required. */
if (!vcall_offset
- || !CONST_OK_FOR_LETTER_P (delta, 'K')
- || !CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
+ || (!DISP_IN_RANGE (delta)
+ && !CONST_OK_FOR_LETTER_P (delta, 'K'))
+ || (!DISP_IN_RANGE (delta)
+ && !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{
op[5] = gen_label_rtx ();
output_asm_insn ("basr\t%4,0", op);
@@ -6558,6 +6848,8 @@
{
if (CONST_OK_FOR_LETTER_P (delta, 'J'))
output_asm_insn ("la\t%1,%2(%1)", op);
+ else if (DISP_IN_RANGE (delta))
+ output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_LETTER_P (delta, 'K'))
output_asm_insn ("ahi\t%1,%2", op);
else
@@ -6575,6 +6867,11 @@
output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("a\t%1,%3(%4)", op);
}
+ else if (DISP_IN_RANGE (vcall_offset))
+ {
+ output_asm_insn ("lg\t%4,0(%1)", op);
+ output_asm_insn ("ay\t%1,%3(%4)", op);
+ }
else if (CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
{
output_asm_insn ("lhi\t%4,%3", op);
--- gcc-3.3.4/gcc/config/s390/s390.h.orig 2003-11-06 16:53:07.000000000 -0500
+++ gcc-3.3.4/gcc/config/s390/s390.h 2004-06-23 14:31:36.000000000 -0400
@@ -28,6 +28,42 @@
#include <s390/fixdfdi.h>
#endif
+/* Which processor to generate code or schedule for. The cpu attribute
+ defines a list that mirrors this list, so changes to s390.md must be
+ made at the same time. */
+
+enum processor_type
+{
+ PROCESSOR_9672_G5,
+ PROCESSOR_9672_G6,
+ PROCESSOR_2064_Z900,
+ PROCESSOR_2084,
+ PROCESSOR_max
+};
+
+/* Optional architectural facilities supported by the processor. */
+
+enum processor_flags
+{
+ PF_IEEE_FLOAT = 1,
+ PF_ZARCH = 2,
+ PF_LONG_DISPLACEMENT = 4
+};
+
+extern enum processor_type s390_tune;
+extern enum processor_flags s390_tune_flags;
+extern const char *s390_tune_string;
+
+extern enum processor_type s390_arch;
+extern enum processor_flags s390_arch_flags;
+extern const char *s390_arch_string;
+
+#define TARGET_CPU_IEEE_FLOAT \
+ (s390_arch_flags & PF_IEEE_FLOAT)
+#define TARGET_CPU_ZARCH \
+ (s390_arch_flags & PF_ZARCH)
+#define TARGET_LONG_DISPLACEMENT \
+ (TARGET_ZARCH && (s390_arch_flags & PF_LONG_DISPLACEMENT))
/* Run-time target specification. */
@@ -46,39 +82,57 @@
/* Optional target features. */
extern int target_flags;
-#define TARGET_HARD_FLOAT (target_flags & 1)
-#define TARGET_SOFT_FLOAT (!(target_flags & 1))
-#define TARGET_BACKCHAIN (target_flags & 2)
-#define TARGET_SMALL_EXEC (target_flags & 4)
-#define TARGET_DEBUG_ARG (target_flags & 8)
-#define TARGET_64BIT (target_flags & 16)
-#define TARGET_MVCLE (target_flags & 32)
+#define MASK_HARD_FLOAT 0x01
+#define MASK_BACKCHAIN 0x02
+#define MASK_SMALL_EXEC 0x04
+#define MASK_DEBUG_ARG 0x08
+#define MASK_64BIT 0x10
+#define MASK_ZARCH 0x20
+#define MASK_MVCLE 0x40
+
+#define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
+#define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
+#define TARGET_BACKCHAIN (target_flags & MASK_BACKCHAIN)
+#define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC)
+#define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
+#define TARGET_64BIT (target_flags & MASK_64BIT)
+#define TARGET_ZARCH (target_flags & MASK_ZARCH)
+#define TARGET_MVCLE (target_flags & MASK_MVCLE)
/* ??? Once this actually works, it could be made a runtime option. */
#define TARGET_IBM_FLOAT 0
#define TARGET_IEEE_FLOAT 1
#ifdef DEFAULT_TARGET_64BIT
-#define TARGET_DEFAULT 0x13
+#define TARGET_DEFAULT 0x33
#else
#define TARGET_DEFAULT 0x3
#endif
-#define TARGET_SWITCHES \
-{ { "hard-float", 1, N_("Use hardware fp")}, \
- { "soft-float", -1, N_("Don't use hardware fp")}, \
- { "backchain", 2, N_("Set backchain")}, \
+#define TARGET_SWITCHES \
+{ { "hard-float", 1, N_("Use hardware fp")}, \
+ { "soft-float", -1, N_("Don't use hardware fp")}, \
+ { "backchain", 2, N_("Set backchain")}, \
{ "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \
- { "small-exec", 4, N_("Use bras for executable < 64k")}, \
- { "no-small-exec",-4, N_("Don't use bras")}, \
- { "debug", 8, N_("Additional debug prints")}, \
- { "no-debug", -8, N_("Don't print additional debug prints")}, \
- { "64", 16, N_("64 bit mode")}, \
- { "31", -16, N_("31 bit mode")}, \
- { "mvcle", 32, N_("mvcle use")}, \
- { "no-mvcle", -32, N_("mvc&ex")}, \
+ { "small-exec", 4, N_("Use bras for execucable < 64k")}, \
+ { "no-small-exec",-4, N_("Don't use bras")}, \
+ { "debug", 8, N_("Additional debug prints")}, \
+ { "no-debug", -8, N_("Don't print additional debug prints")}, \
+ { "64", 16, N_("64 bit ABI")}, \
+ { "31", -16, N_("31 bit ABI")}, \
+ { "zarch", 32, N_("z/Architecture")}, \
+ { "esa", -32, N_("ESA/390 architecture")}, \
+ { "mvcle", 64, N_("mvcle use")}, \
+ { "no-mvcle", -64, N_("mvc&ex")}, \
{ "", TARGET_DEFAULT, 0 } }
+#define TARGET_OPTIONS \
+{ { "tune=", &s390_tune_string, \
+ N_("Schedule code for given CPU")}, \
+ { "arch=", &s390_arch_string, \
+ N_("Generate code for given CPU")}, \
+}
+
/* Target version string. Overridden by the OS header. */
#ifdef DEFAULT_TARGET_64BIT
#define TARGET_VERSION fprintf (stderr, " (zSeries)");
@@ -453,10 +507,11 @@
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'Q' ? q_constraint (OP) : \
- (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0)
-
-#define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'Q')
+ s390_extra_constraint ((OP), (C))
+#define EXTRA_MEMORY_CONSTRAINT(C) \
+ ((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
+#define EXTRA_ADDRESS_CONSTRAINT(C) \
+ ((C) == 'U' || (C) == 'W')
/* Stack layout and calling conventions. */
--- gcc-3.3.4/gcc/config/s390/s390.md.orig 2004-03-06 21:48:02.000000000 -0500
+++ gcc-3.3.4/gcc/config/s390/s390.md 2004-06-23 14:31:37.000000000 -0400
@@ -73,18 +73,53 @@
])
+;; Processor type. This attribute must exactly match the processor_type
+;; enumeration in s390.h.
+
+(define_attr "cpu" "g5,g6,z900,z990"
+ (const (symbol_ref "s390_tune")))
+
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
- (const_string "integer"))
+(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
+ cs,vs,store,imul,idiv,
+ branch,jsr,fsimpd,fsimps,
+ floadd,floads,fstored, fstores,
+ fmuld,fmuls,fdivd,fdivs,
+ ftoi,itof,fsqrtd,fsqrts,
+ other,o2,o3"
+ (const_string "integer"))
+
+;; Operand type. Used to default length attribute values
+
+(define_attr "op_type"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
+ (const_string "RX"))
;; Insn are devide in two classes:
-;; mem: Insn accessing memory
-;; reg: Insn operands all in registers
+;; agen: Insn using agen
+;; reg: Insn not using agen
-(define_attr "atype" "reg,mem"
- (const_string "reg"))
+(define_attr "atype" "agen,reg"
+(cond [ (eq_attr "op_type" "E") (const_string "reg")
+ (eq_attr "op_type" "RR") (const_string "reg")
+ (eq_attr "op_type" "RX") (const_string "agen")
+ (eq_attr "op_type" "RI") (const_string "reg")
+ (eq_attr "op_type" "RRE") (const_string "reg")
+ (eq_attr "op_type" "RS") (const_string "agen")
+ (eq_attr "op_type" "RSI") (const_string "agen")
+ (eq_attr "op_type" "S") (const_string "agen")
+ (eq_attr "op_type" "SI") (const_string "agen")
+ (eq_attr "op_type" "SS") (const_string "agen")
+ (eq_attr "op_type" "SSE") (const_string "agen")
+ (eq_attr "op_type" "RXE") (const_string "agen")
+ (eq_attr "op_type" "RSE") (const_string "agen")
+ (eq_attr "op_type" "RIL") (const_string "agen")
+ (eq_attr "op_type" "RXY") (const_string "agen")
+ (eq_attr "op_type" "RSY") (const_string "agen")
+ (eq_attr "op_type" "SIY") (const_string "agen")]
+ (const_string "reg")))
;; Generic pipeline function unit.
@@ -95,18 +130,42 @@
(eq_attr "type" "integer") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsimpd") 1 1)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsimps") 1 1)
+
+(define_function_unit "integer" 1 0
(eq_attr "type" "load") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "floadd") 1 1)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "floads") 1 1)
+
+(define_function_unit "integer" 1 0
(eq_attr "type" "la") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "larl") 1 1)
+
+(define_function_unit "integer" 1 0
(eq_attr "type" "lr") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "branch") 1 1)
+
+(define_function_unit "integer" 1 0
(eq_attr "type" "store") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "fstored") 1 1)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fstores") 1 1)
+
+(define_function_unit "integer" 1 0
(eq_attr "type" "lm") 2 2)
(define_function_unit "integer" 1 0
@@ -125,13 +184,31 @@
(eq_attr "type" "imul") 7 7)
(define_function_unit "integer" 1 0
- (eq_attr "type" "fmul") 6 6)
+ (eq_attr "type" "fmuld") 6 6)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fmuls") 6 6)
(define_function_unit "integer" 1 0
(eq_attr "type" "idiv") 33 33)
(define_function_unit "integer" 1 0
- (eq_attr "type" "fdiv") 33 33)
+ (eq_attr "type" "fdivd") 33 33)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fdivs") 33 33)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsqrtd") 30 30)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsqrts") 30 30)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "ftoi") 2 2)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "itof") 2 2)
(define_function_unit "integer" 1 0
(eq_attr "type" "o2") 2 2)
@@ -142,11 +219,10 @@
(define_function_unit "integer" 1 0
(eq_attr "type" "other") 5 5)
-;; Operand type. Used to default length attribute values
+;; Pipeline description for z900
-(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
- (const_string "RX"))
+(include "2064.md")
+(include "2084.md")
;; Length in bytes.
@@ -158,14 +234,16 @@
(eq_attr "op_type" "RRE") (const_int 4)
(eq_attr "op_type" "RS") (const_int 4)
(eq_attr "op_type" "RSI") (const_int 4)
- (eq_attr "op_type" "RX") (const_int 4)
(eq_attr "op_type" "S") (const_int 4)
(eq_attr "op_type" "SI") (const_int 4)
(eq_attr "op_type" "SS") (const_int 6)
(eq_attr "op_type" "SSE") (const_int 6)
(eq_attr "op_type" "RXE") (const_int 6)
(eq_attr "op_type" "RSE") (const_int 6)
- (eq_attr "op_type" "RIL") (const_int 6)]
+ (eq_attr "op_type" "RIL") (const_int 6)
+ (eq_attr "op_type" "RXY") (const_int 6)
+ (eq_attr "op_type" "RSY") (const_int 6)
+ (eq_attr "op_type" "SIY") (const_int 6)]
(const_int 4)))
;; Define attributes for `asm' insns.
@@ -306,9 +384,9 @@
(define_insn "*tmqi_ext"
[(set (reg 33)
- (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
- (match_operand:SI 1 "const_int_operand" "n")
- (match_operand:SI 2 "const_int_operand" "n"))
+ (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:SI 1 "const_int_operand" "n,n")
+ (match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
@@ -319,18 +397,17 @@
int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
operands[2] = GEN_INT (block << shift);
- return \"tm\\t%0,%b2\";
+ return which_alternative == 0 ? \"tm\\t%0,%b2\" : \"tmy\\t%0,%b2\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SIY")])
; Test-under-Mask instructions
(define_insn "*tmdi_mem"
[(set (reg 33)
- (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
- (match_operand:DI 1 "immediate_operand" "n"))
- (match_operand:DI 2 "immediate_operand" "n")))]
+ (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
+ (match_operand:DI 1 "immediate_operand" "n,n"))
+ (match_operand:DI 2 "immediate_operand" "n,n")))]
"TARGET_64BIT
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], DImode, 0) >= 0"
@@ -341,16 +418,15 @@
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
+ return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmsi_mem"
[(set (reg 33)
- (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
- (match_operand:SI 1 "immediate_operand" "n"))
- (match_operand:SI 2 "immediate_operand" "n")))]
+ (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S")
+ (match_operand:SI 1 "immediate_operand" "n,n"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], SImode, 0) >= 0"
"*
@@ -360,16 +436,15 @@
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
+ return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem"
[(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
- (match_operand:SI 1 "immediate_operand" "n"))
- (match_operand:SI 2 "immediate_operand" "n")))]
+ (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0)
+ (match_operand:SI 1 "immediate_operand" "n,n"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], HImode, 0) >= 0"
"*
@@ -379,20 +454,20 @@
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
- return \"tm\\t%0,%b1\";
+ return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem"
[(set (reg 33)
- (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
- (match_operand:SI 1 "immediate_operand" "n"))
- (match_operand:SI 2 "immediate_operand" "n")))]
+ (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0)
+ (match_operand:SI 1 "immediate_operand" "n,n"))
+ (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
- "tm\\t%0,%b1"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ "@
+ tm\\t%0,%b1
+ tmy\\t%0,%b1"
+ [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
[(set (reg 33)
@@ -493,32 +568,34 @@
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
"srda\\t%0,0"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
+
(define_insn "*tstsi"
[(set (reg 33)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
- (set (match_operand:SI 2 "register_operand" "=d,d")
+ (set (match_operand:SI 2 "register_operand" "=d,d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%2,%0
- icm\\t%2,15,%0"
- [(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
+ icm\\t%2,15,%0
+ icmy\\t%2,15,%0"
+ [(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
- (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
+ (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" "")))
- (clobber (match_scratch:SI 2 "=X,d"))]
+ (clobber (match_scratch:SI 2 "=X,d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%0,%0
- icm\\t%2,15,%0"
- [(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
+ icm\\t%2,15,%0
+ icmy\\t%2,15,%0"
+ [(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
@@ -530,94 +607,98 @@
(define_insn "*tsthiCCT"
[(set (reg 33)
- (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
+ (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d,0")
+ (set (match_operand:HI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
+ icmy\\t%2,3,%0
tml\\t%0,65535"
- [(set_attr "op_type" "RS,RI")
- (set_attr "atype" "mem,reg")])
+ [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly"
[(set (reg 33)
- (compare (match_operand:HI 0 "nonimmediate_operand" "Q,d")
+ (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
(match_operand:HI 1 "const0_operand" "")))
- (clobber (match_scratch:HI 2 "=d,X"))]
+ (clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
+ icmy\\t%2,3,%0
tml\\t%0,65535"
- [(set_attr "op_type" "RS,RI")
- (set_attr "atype" "mem,reg")])
+ [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthi"
[(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q")
+ (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" "")))
- (set (match_operand:HI 2 "register_operand" "=d")
+ (set (match_operand:HI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%2,3,%0
+ icmy\\t%2,3,%0"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
- (compare (match_operand:HI 0 "s_operand" "Q")
+ (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" "")))
- (clobber (match_scratch:HI 2 "=d"))]
+ (clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%2,3,%0
+ icmy\\t%2,3,%0"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT"
[(set (reg 33)
- (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d,0")
+ (set (match_operand:QI 2 "register_operand" "=d,d,0")
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,1,%0
+ icmy\\t%2,1,%0
tml\\t%0,255"
- [(set_attr "op_type" "RS,RI")
- (set_attr "atype" "mem,reg")])
+ [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tstqiCCT_cconly"
[(set (reg 33)
- (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
cli\\t%0,0
+ cliy\\t%0,0
tml\\t%0,255"
- [(set_attr "op_type" "SI,RI")
- (set_attr "atype" "mem,reg")])
+ [(set_attr "op_type" "SI,SIY,RI")])
(define_insn "*tstqi"
[(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q")
+ (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" "")))
- (set (match_operand:QI 2 "register_operand" "=d")
+ (set (match_operand:QI 2 "register_operand" "=d,d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%2,1,%0
+ icmy\\t%2,1,%0"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
- (compare (match_operand:QI 0 "s_operand" "Q")
+ (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" "")))
- (clobber (match_scratch:QI 2 "=d"))]
+ (clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
- "icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%2,1,%0
+ icmy\\t%2,1,%0"
+ [(set_attr "op_type" "RS,RSY")])
; Compare (signed) instructions
@@ -630,8 +711,7 @@
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
@@ -642,29 +722,29 @@
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
- [(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")])
+ [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
- (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
- (match_operand:SI 0 "register_operand" "d")))]
+ (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
+ (match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
- "ch\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ ch\\t%0,%1
+ chy\\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d,d")
- (match_operand:SI 1 "general_operand" "d,K,m")))]
+ (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
+ (match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\\t%0,%1
chi\\t%0,%c1
- c\\t%0,%1"
- [(set_attr "op_type" "RR,RI,RX")
- (set_attr "atype" "reg,reg,mem")])
+ c\\t%0,%1
+ cy\\t%0,%1"
+ [(set_attr "op_type" "RR,RI,RX,RXY")])
; Compare (unsigned) instructions
@@ -677,8 +757,7 @@
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
@@ -688,46 +767,48 @@
"@
clgr\\t%0,%1
clg\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
- (compare (match_operand:SI 0 "register_operand" "d,d")
- (match_operand:SI 1 "general_operand" "d,m")))]
+ (compare (match_operand:SI 0 "register_operand" "d,d,d")
+ (match_operand:SI 1 "general_operand" "d,R,T")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clr\\t%0,%1
- cl\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ cl\\t%0,%1
+ cly\\t%0,%1"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
- (compare (match_operand:HI 0 "register_operand" "d")
- (match_operand:HI 1 "s_imm_operand" "Q")))]
+ (compare (match_operand:HI 0 "register_operand" "d,d")
+ (match_operand:HI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
- "clm\\t%0,3,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ clm\\t%0,3,%1
+ clmy\\t%0,3,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
- (compare (match_operand:QI 0 "register_operand" "d")
- (match_operand:QI 1 "s_imm_operand" "Q")))]
+ (compare (match_operand:QI 0 "register_operand" "d,d")
+ (match_operand:QI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
- "clm\\t%0,1,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ clm\\t%0,1,%1
+ clmy\\t%0,1,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*cli"
[(set (reg 33)
- (compare (match_operand:QI 0 "memory_operand" "Q")
- (match_operand:QI 1 "immediate_operand" "n")))]
+ (compare (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:QI 1 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, CCUmode)"
- "cli\\t%0,%b1"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ "@
+ cli\\t%0,%b1
+ cliy\\t%0,%b1"
+ [(set_attr "op_type" "SI,SIY")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
@@ -735,8 +816,7 @@
(match_operand:DI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*cmpsi_ccu_mem"
[(set (reg 33)
@@ -744,8 +824,7 @@
(match_operand:SI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*cmphi_ccu_mem"
[(set (reg 33)
@@ -753,8 +832,7 @@
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*cmpqi_ccu_mem"
[(set (reg 33)
@@ -762,8 +840,7 @@
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
; DF instructions
@@ -774,7 +851,8 @@
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltdbr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs_0_ibm"
[(set (reg 33)
@@ -782,29 +860,30 @@
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"ltdr\\t%0,%0"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,m")))]
+ (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cdbr\\t%0,%1
cdb\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f")
- (match_operand:DF 1 "general_operand" "f,m")))]
+ (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cdr\\t%0,%1
cd\\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd")])
; SF instructions
@@ -815,7 +894,8 @@
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltebr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs_0_ibm"
[(set (reg 33)
@@ -823,29 +903,30 @@
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lter\\t%0,%0"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,m")))]
+ (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cebr\\t%0,%1
ceb\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f")
- (match_operand:SF 1 "general_operand" "f,m")))]
+ (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cer\\t%0,%1
ce\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")
+ (set_attr "type" "fsimps")])
;;
@@ -857,8 +938,8 @@
;
(define_insn "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q")
- (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
+ (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
lmg\\t%0,%N0,%1
@@ -866,8 +947,8 @@
#
#
mvc\\t%O0(16,%R0),%1"
- [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
+ (set_attr "type" "lm,stm,*,*,cs")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -952,8 +1033,7 @@
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
&& !FP_REG_P (operands[0])"
"lghi\\t%0,%h1"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*movdi_lli"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -974,8 +1054,18 @@
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
+
+(define_insn "*movdi_lay"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (match_operand:DI 1 "address_operand" "p"))]
+ "TARGET_64BIT
+ && TARGET_LONG_DISPLACEMENT
+ && GET_CODE (operands[1]) == CONST_INT
+ && !FP_REG_P (operands[0])"
+ "lay\\t%0,%a1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "type" "la")])
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -984,12 +1074,11 @@
&& !FP_REG_P (operands[0])"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "atype" "reg")
- (set_attr "type" "la")])
+ (set_attr "type" "larl")])
(define_insn "*movdi_64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
- (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q")
+ (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT"
"@
lgr\\t%0,%1
@@ -997,14 +1086,16 @@
stg\\t%1,%0
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
(define_insn "*movdi_31"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q")
- (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
+ (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
lm\\t%0,%N0,%1
@@ -1013,10 +1104,12 @@
#
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
- (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -1147,20 +1240,34 @@
}"
[(set_attr "op_type" "RI")])
+(define_insn "*movsi_lay"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (match_operand:SI 1 "address_operand" "p"))]
+ "TARGET_LONG_DISPLACEMENT
+ && GET_CODE (operands[1]) == CONST_INT
+ && !FP_REG_P (operands[0])"
+ "lay\\t%0,%a1"
+ [(set_attr "op_type" "RXY")
+ (set_attr "type" "la")])
+
(define_insn "*movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q")
- (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
+ (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
""
"@
lr\\t%0,%1
l\\t%0,%1
+ ly\\t%0,%1
st\\t%1,%0
+ sty\\t%1,%0
ler\\t%0,%1
le\\t%0,%1
+ ley\\t%0,%1
ste\\t%1,%0
+ stey\\t%1,%0
mvc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
@@ -1178,17 +1285,19 @@
;
(define_insn "movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q")
- (match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
+ (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%h1
lh\\t%0,%1
+ lhy\\t%0,%1
sth\\t%1,%0
+ sthy\\t%1,%0
mvc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "RR,RI,RX,RX,SS")
- (set_attr "atype" "reg,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "lr,*,*,*,store,store,cs")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
@@ -1205,33 +1314,37 @@
;
(define_insn "movqi_64"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
- (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
+ (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
lhi\\t%0,%b1
llgc\\t%0,%1
stc\\t%1,%0
+ stcy\\t%1,%0
mvi\\t%0,%b1
+ mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
- (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
-
+ [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
+ (set_attr "type" "lr,*,*,store,store,store,store,cs")])
(define_insn "movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q")
- (match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
+ (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%b1
ic\\t%0,%1
+ icy\\t%0,%1
stc\\t%1,%0
+ stcy\\t%1,%0
mvi\\t%0,%b1
+ mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
- (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
+ (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -1248,41 +1361,42 @@
;
(define_insn "*movstrictqi"
- [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
- (match_operand:QI 1 "memory_operand" "m"))]
+ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
+ (match_operand:QI 1 "memory_operand" "R,T"))]
""
- "ic\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ ic\\t%0,%1
+ icy\\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")])
;
; movstricthi instruction pattern(s).
;
(define_insn "*movstricthi"
- [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
- (match_operand:HI 1 "s_imm_operand" "Q"))
+ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
+ (match_operand:HI 1 "s_imm_operand" "Q,S"))
(clobber (reg:CC 33))]
""
- "icm\\t%0,3,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
-
+ "@
+ icm\\t%0,3,%1
+ icmy\\t%0,3,%1"
+ [(set_attr "op_type" "RS,RSY")])
;
; movstrictsi instruction pattern(s).
;
(define_insn "movstrictsi"
- [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
- (match_operand:SI 1 "general_operand" "d,m"))]
+ [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
+ (match_operand:SI 1 "general_operand" "d,R,T"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
- l\\t%0,%1"
- [(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
-
+ l\\t%0,%1
+ ly\\t%0,%1"
+ [(set_attr "op_type" "RR,RX,RXY")
+ (set_attr "type" "lr,load,load")])
;
; movdf instruction pattern(s).
@@ -1302,35 +1416,39 @@
}")
(define_insn "*movdf_64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
- (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
+ (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
lgr\\t%0,%1
lg\\t%0,%1
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+ (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
(define_insn "*movdf_31"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q")
- (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
+ (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
+ ldy\\t%0,%1
std\\t%1,%0
+ stdy\\t%1,%0
lm\\t%0,%N0,%1
stm\\t%1,%N1,%0
#
#
mvc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
- (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
+ (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -1403,19 +1521,23 @@
}")
(define_insn "*movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q")
- (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
+ (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
ler\\t%0,%1
le\\t%0,%1
+ ley\\t%0,%1
ste\\t%1,%0
+ stey\\t%1,%0
lr\\t%0,%1
l\\t%0,%1
+ ly\\t%0,%1
st\\t%1,%0
+ sty\\t%1,%0
mvc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+ (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
;
; load_multiple pattern(s).
@@ -1488,39 +1610,29 @@
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
- (match_operand:DI 2 "s_operand" "Q"))])]
+ (match_operand:DI 2 "s_operand" "QS"))])]
"reload_completed"
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"lg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
- return \"lmg\\t%1,%0,%2\";
+ return \"lmg\\t%1,%0,%2\";
}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ [(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
[(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "register_operand" "=r")
- (match_operand:SI 2 "s_operand" "Q"))])]
+ [(set (match_operand:SI 1 "register_operand" "=r,r")
+ (match_operand:SI 2 "s_operand" "Q,S"))])]
"reload_completed"
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"l\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
- return \"lm\\t%1,%0,%2\";
+ return which_alternative == 0 ? \"lm\\t%1,%0,%2\" : \"lmy\\t%1,%0,%2\";
}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ [(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
;
@@ -1591,41 +1703,31 @@
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:DI 1 "s_operand" "=Q")
+ [(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
"reload_completed"
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"stg\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
- return \"stmg\\t%2,%0,%1\";
+ return \"stmg\\t%2,%0,%1\";
}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ [(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
(define_insn "*store_multiple_si"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:SI 1 "s_operand" "=Q")
- (match_operand:SI 2 "register_operand" "r"))])]
+ [(set (match_operand:SI 1 "s_operand" "=Q,S")
+ (match_operand:SI 2 "register_operand" "r,r"))])]
"reload_completed"
"*
{
int words = XVECLEN (operands[0], 0);
-
- if (XVECLEN (operands[0], 0) == 1)
- return \"st\\t%1,0(%2)\";
-
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
- return \"stm\\t%2,%0,%1\";
+ return which_alternative == 0 ? \"stm\\t%2,%0,%1\" : \"stmy\\t%2,%0,%1\";
}"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
+ [(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
;;
@@ -1679,7 +1781,7 @@
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "movstr_short_31"
@@ -1706,7 +1808,7 @@
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Move a block of arbitrary length.
@@ -1727,7 +1829,6 @@
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
- (set_attr "atype" "mem")
(set_attr "length" "8")])
(define_insn "movstr_long_31"
@@ -1746,7 +1847,6 @@
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
- (set_attr "atype" "mem")
(set_attr "length" "8")])
;
@@ -1797,7 +1897,7 @@
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "clrstr_short_31"
@@ -1825,7 +1925,7 @@
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Clear a block of arbitrary length.
@@ -1842,7 +1942,6 @@
"TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
@@ -1858,7 +1957,6 @@
"!TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
@@ -1914,7 +2012,7 @@
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "cmpstr_short_31"
@@ -1942,7 +2040,7 @@
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Compare a block of arbitrary length.
@@ -1958,7 +2056,6 @@
"TARGET_64BIT"
"clcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
@@ -1973,7 +2070,6 @@
"!TARGET_64BIT"
"clcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
@@ -1993,7 +2089,6 @@
}"
[(set_attr "op_type" "NN")
(set_attr "length" "16")
- (set_attr "atype" "reg")
(set_attr "type" "other")])
(define_insn "cmpint_di"
@@ -2010,7 +2105,6 @@
}"
[(set_attr "op_type" "NN")
(set_attr "length" "20")
- (set_attr "atype" "reg")
(set_attr "type" "other")])
@@ -2019,40 +2113,42 @@
;;
(define_insn "*sethighqisi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
""
- "icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%0,8,%1
+ icmy\\t%0,8,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
""
- "icm\\t%0,12,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%0,12,%1
+ icmy\\t%0,12,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
+ (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] 10))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
- "icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ "@
+ icm\\t%0,8,%1
+ icmy\\t%0,8,%1"
+ [(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -2073,7 +2169,7 @@
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
operands[1] = change_address (operands[1], QImode, 0);
}"
- [(set_attr "atype" "mem")])
+ [(set_attr "atype" "agen")])
(define_insn_and_split "*extracthi"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -2094,7 +2190,7 @@
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
operands[1] = change_address (operands[1], HImode, 0);
}"
- [(set_attr "atype" "mem")])
+ [(set_attr "atype" "agen")])
;
; extendsidi2 instruction pattern(s).
@@ -2124,8 +2220,7 @@
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
;
; extendhidi2 instruction pattern(s).
@@ -2159,8 +2254,7 @@
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXY")])
;
; extendqidi2 instruction pattern(s).
@@ -2189,10 +2283,17 @@
}
")
+(define_insn "*extendqidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "lgb\\t%0,%1"
+ [(set_attr "op_type" "RXY")])
+
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
- "TARGET_64BIT && !reload_completed"
+ "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
@@ -2219,12 +2320,13 @@
")
(define_insn "*extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
""
- "lh\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ lh\\t%0,%1
+ lhy\\t%0,%1"
+ [(set_attr "op_type" "RX,RXY")])
;
; extendqisi2 instruction pattern(s).
@@ -2243,10 +2345,17 @@
}
")
+(define_insn "*extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+ "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "lb\\t%0,%1"
+ [(set_attr "op_type" "RXY")])
+
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
- "!reload_completed"
+ "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
@@ -2287,8 +2396,7 @@
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
;
; zero_extendhidi2 instruction pattern(s).
@@ -2322,8 +2430,7 @@
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXY")])
;
; zero_extendqidi2 instruction pattern(s)
@@ -2357,8 +2464,7 @@
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXY")])
;
; zero_extendhisi2 instruction pattern(s).
@@ -2381,12 +2487,11 @@
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
+ (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"#"
@@ -2396,7 +2501,7 @@
[(set (strict_low_part (match_dup 2)) (match_dup 1))
(clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);"
- [(set_attr "atype" "mem")])
+ [(set_attr "atype" "agen")])
;
; zero_extendqisi2 instruction pattern(s).
@@ -2419,8 +2524,7 @@
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
@@ -2431,7 +2535,7 @@
[(set (match_dup 0) (const_int 0))
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
- [(set_attr "atype" "mem")])
+ [(set_attr "atype" "agen")])
;
; zero_extendqihi2 instruction pattern(s).
@@ -2454,8 +2558,7 @@
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
@@ -2466,7 +2569,7 @@
[(set (match_dup 0) (const_int 0))
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
- [(set_attr "atype" "mem")])
+ [(set_attr "atype" "agen")])
;
@@ -2519,7 +2622,7 @@
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgdbr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
+ (set_attr "type" "ftoi")])
;
; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
@@ -2606,7 +2709,8 @@
return \"l\\t%0,%N4\";
}"
[(set_attr "op_type" "NN")
- (set_attr "type" "other")
+ (set_attr "type" "ftoi")
+ (set_attr "atype" "agen")
(set_attr "length" "20")])
;
@@ -2660,7 +2764,7 @@
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
+ (set_attr "type" "ftoi")])
;
; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
@@ -2723,7 +2827,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
+ (set_attr "type" "ftoi")])
;
; floatdidf2 instruction pattern(s).
@@ -2736,7 +2840,7 @@
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdgbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
;
; floatdisf2 instruction pattern(s).
@@ -2749,7 +2853,7 @@
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cegbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
;
; floatsidf2 instruction pattern(s).
@@ -2782,7 +2886,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
(define_insn "floatsidf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -2801,6 +2905,7 @@
}"
[(set_attr "op_type" "NN")
(set_attr "type" "other" )
+ (set_attr "atype" "agen")
(set_attr "length" "20")])
;
@@ -2832,7 +2937,7 @@
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
;
; truncdfsf2 instruction pattern(s).
@@ -2853,13 +2958,13 @@
(define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
+ (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
lrer\\t%0,%1
le\\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "floads,floads")])
;
; extendsfdf2 instruction pattern(s).
@@ -2880,23 +2985,25 @@
(define_insn "extendsfdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ldebr\\t%0,%1
ldeb\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "floads,floads")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
sdr\\t%0,%0\;ler\\t%0,%1
sdr\\t%0,%0\;le\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")
+ [(set_attr "op_type" "NN,NN")
+ (set_attr "atype" "reg,agen")
+ (set_attr "length" "4,6")
(set_attr "type" "o2,o2")])
@@ -2924,8 +3031,7 @@
"@
agfr\\t%0,%2
agf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
@@ -2938,8 +3044,7 @@
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
@@ -2951,8 +3056,7 @@
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -2963,8 +3067,7 @@
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
@@ -2977,8 +3080,7 @@
&& s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*adddi3_cc"
[(set (reg 33)
@@ -2991,8 +3093,7 @@
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
@@ -3004,8 +3105,7 @@
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
@@ -3016,8 +3116,7 @@
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
@@ -3029,8 +3128,7 @@
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")])
+ [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
@@ -3075,12 +3173,13 @@
"")
(define_insn "*la_64"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:QI 1 "address_operand" "p"))]
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "U,W"))]
"TARGET_64BIT"
- "la\\t%0,%a1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_peephole2
@@ -3135,142 +3234,144 @@
"s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"ahi\\t%0,%h2"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
- (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
- (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
alr\\t%0,%2
- al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ al\\t%0,%2
+ aly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (match_operand:SI 1 "register_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (plus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))]
""
- "ah\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ ah\\t%0,%2
+ ahy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "*addsi3_sub"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (plus:SI (match_operand:SI 1 "register_operand" "0")
- (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (plus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))]
""
- "ah\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ ah\\t%0,%2
+ ahy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "addsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,R,T")))
(clobber (reg:CC 33))]
""
"@
ar\\t%0,%2
ahi\\t%0,%h2
- a\\t%0,%2"
- [(set_attr "op_type" "RR,RI,RX")
- (set_attr "atype" "reg,reg,mem")])
+ a\\t%0,%2
+ ay\\t%0,%2"
+ [(set_attr "op_type" "RR,RI,RX,RXY")])
(define_insn "*la_31"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:QI 1 "address_operand" "p"))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "U,W"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
- "la\\t%0,%a1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_peephole2
@@ -3300,13 +3401,14 @@
"")
(define_insn "*la_31_and"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (and:SI (match_operand:QI 1 "address_operand" "p")
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:QI 1 "address_operand" "U,W")
(const_int 2147483647)))]
"!TARGET_64BIT"
- "la\\t%0,%a1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
+ [(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc"
@@ -3321,17 +3423,17 @@
(and:SI (match_dup 1) (const_int 2147483647)))]
""
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn "force_la_31"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (match_operand:QI 1 "address_operand" "p"))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (match_operand:QI 1 "address_operand" "U,W"))
(use (const_int 0))]
"!TARGET_64BIT"
- "la\\t%0,%a1"
+ "@
+ la\\t%0,%a1
+ lay\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_expand "reload_insi"
@@ -3354,7 +3456,7 @@
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -3362,26 +3464,26 @@
(define_insn "*adddf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
adbr\\t%0,%2
adb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
adr\\t%0,%2
ad\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
;
; addsf3 instruction pattern(s).
@@ -3391,7 +3493,7 @@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -3399,26 +3501,26 @@
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
aebr\\t%0,%2
aeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
aer\\t%0,%2
ae\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
;;
@@ -3438,8 +3540,7 @@
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
@@ -3452,8 +3553,7 @@
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
@@ -3465,8 +3565,7 @@
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3477,8 +3576,7 @@
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
[(set (reg 33)
@@ -3491,8 +3589,7 @@
"@
slgr\\t%0,%2
slg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
@@ -3504,8 +3601,7 @@
"@
slgr\\t%0,%2
slg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3516,8 +3612,7 @@
"@
sgr\\t%0,%2
sg\\t%0,%2"
- [(set_attr "op_type" "RRE,RRE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RRE")])
(define_insn_and_split "*subdi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
@@ -3567,89 +3662,91 @@
(define_insn "*subsi3_borrow_cc"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXE")])
(define_insn "*subsi3_cc"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
- (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
- sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ sl\\t%0,%2
+ sly\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_sign"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (match_operand:SI 1 "register_operand" "0")
- (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))]
""
- "sh\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ sh\\t%0,%2
+ shy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "*subsi3_sub"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (minus:SI (match_operand:SI 1 "register_operand" "0")
- (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0")
+ (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))]
""
- "sh\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ sh\\t%0,%2
+ shy\\t%0,%2"
+ [(set_attr "op_type" "RX,RXY")])
(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (minus:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
sr\\t%0,%2
- s\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ s\\t%0,%2
+ sy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
;
@@ -3660,7 +3757,7 @@
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -3668,26 +3765,26 @@
(define_insn "*subdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sdbr\\t%0,%2
sdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
sdr\\t%0,%2
sd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
;
; subsf3 instruction pattern(s).
@@ -3697,7 +3794,7 @@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -3705,26 +3802,26 @@
(define_insn "*subsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sebr\\t%0,%2
seb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
ser\\t%0,%2
se\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
;;
@@ -3743,8 +3840,7 @@
"@
msgfr\\t%0,%2
msgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")
+ [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")])
@@ -3757,8 +3853,7 @@
msgr\\t%0,%2
mghi\\t%0,%h2
msg\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")
+ [(set_attr "op_type" "RRE,RI,RXY")
(set_attr "type" "imul")])
;
@@ -3766,16 +3861,16 @@
;
(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,m")))]
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,R,T")))]
""
"@
msr\\t%0,%2
mhi\\t%0,%h2
- ms\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RX")
- (set_attr "atype" "reg,reg,mem")
+ ms\\t%0,%2
+ msy\\t%0,%2"
+ [(set_attr "op_type" "RRE,RI,RX,RXY")
(set_attr "type" "imul")])
;
@@ -3808,13 +3903,12 @@
(mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+ (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT"
"@
mr\\t%0,%2
m\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")
(set_attr "type" "imul")])
;
@@ -3825,7 +3919,7 @@
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -3833,28 +3927,26 @@
(define_insn "*muldf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
mdbr\\t%0,%2
mdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuld")])
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
mdr\\t%0,%2
md\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuld")])
;
; mulsf3 instruction pattern(s).
@@ -3864,7 +3956,7 @@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -3872,28 +3964,26 @@
(define_insn "*mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
meebr\\t%0,%2
meeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuls")])
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
mer\\t%0,%2
me\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuls")])
;;
@@ -3958,9 +4048,8 @@
"@
dsgr\\t%0,%2
dsg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "idiv")])
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
@@ -3977,9 +4066,8 @@
"@
dsgfr\\t%0,%2
dsgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "idiv")])
;
; udivmoddi4 instruction pattern(s).
@@ -4040,9 +4128,8 @@
"@
dlgr\\t%0,%2
dlg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "idiv")])
;
; divmodsi4 instruction pattern(s).
@@ -4091,7 +4178,7 @@
(truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(ashift:DI
(zero_extend:DI
(truncate:SI
@@ -4102,8 +4189,7 @@
dr\\t%0,%2
d\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "idiv")])
;
; udivsi3 and umodsi3 instruction pattern(s).
@@ -4302,7 +4388,7 @@
[(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -4310,28 +4396,26 @@
(define_insn "*divdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ddbr\\t%0,%2
ddb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivd")])
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0")
- (match_operand:DF 2 "general_operand" "f,m")))
+ (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
ddr\\t%0,%2
dd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivd")])
;
; divsf3 instruction pattern(s).
@@ -4341,7 +4425,7 @@
[(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT"
"")
@@ -4349,28 +4433,26 @@
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
debr\\t%0,%2
deb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivs")])
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0")
- (match_operand:SF 2 "general_operand" "f,m")))
+ (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
der\\t%0,%2
de\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivs")])
;;
@@ -4392,8 +4474,7 @@
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
@@ -4405,8 +4486,7 @@
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -4428,8 +4508,7 @@
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -4440,8 +4519,7 @@
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
@@ -4450,8 +4528,7 @@
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*anddi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
@@ -4460,8 +4537,7 @@
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; andsi3 instruction pattern(s).
@@ -4469,30 +4545,30 @@
(define_insn "*andsi3_cc"
[(set (reg 33)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
- n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ n\\t%0,%2
+ ny\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
- n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ n\\t%0,%2
+ ny\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -4512,20 +4588,19 @@
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
nr\\t%0,%2
- n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ n\\t%0,%2
+ ny\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
@@ -4534,8 +4609,7 @@
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*andsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
@@ -4544,8 +4618,7 @@
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; andhi3 instruction pattern(s).
@@ -4560,8 +4633,7 @@
"@
nr\\t%0,%2
nill\\t%0,%x2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "andhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
@@ -4570,8 +4642,7 @@
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*andhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
@@ -4580,8 +4651,7 @@
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*andhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
@@ -4590,8 +4660,7 @@
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; andqi3 instruction pattern(s).
@@ -4606,8 +4675,7 @@
"@
nr\\t%0,%2
nill\\t%0,%b2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "andqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
@@ -4616,32 +4684,31 @@
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(and:QI (match_dup 0)
- (match_operand:QI 1 "s_imm_operand" "n,Q")))
+ (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
+ niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*andqi3_ss_inv"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
- (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
+ (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
+ niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SIY,SS")])
;;
@@ -4663,8 +4730,7 @@
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
@@ -4676,8 +4742,7 @@
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -4699,8 +4764,7 @@
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -4711,8 +4775,7 @@
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
@@ -4721,8 +4784,7 @@
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*iordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
@@ -4731,8 +4793,7 @@
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; iorsi3 instruction pattern(s).
@@ -4740,30 +4801,30 @@
(define_insn "*iorsi3_cc"
[(set (reg 33)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
- o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ o\\t%0,%2
+ oy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
- o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ o\\t%0,%2
+ oy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
@@ -4783,20 +4844,19 @@
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
or\\t%0,%2
- o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ o\\t%0,%2
+ oy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
@@ -4805,8 +4865,7 @@
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*iorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
@@ -4815,8 +4874,7 @@
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; iorhi3 instruction pattern(s).
@@ -4831,8 +4889,7 @@
"@
or\\t%0,%2
oill\\t%0,%x2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "iorhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
@@ -4841,8 +4898,7 @@
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*iorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
@@ -4851,8 +4907,7 @@
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*iorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
@@ -4861,8 +4916,7 @@
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; iorqi3 instruction pattern(s).
@@ -4877,8 +4931,7 @@
"@
or\\t%0,%2
oill\\t%0,%b2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "iorqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
@@ -4887,32 +4940,31 @@
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(ior:QI (match_dup 0)
- (match_operand:QI 1 "s_imm_operand" "n,Q")))
+ (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
+ oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*iorqi3_ss_inv"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
- (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
+ (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
+ oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "SI,SIY,SS")])
;;
@@ -4934,8 +4986,7 @@
"@
xgr\\t%0,%2
xg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
@@ -4947,8 +4998,7 @@
"@
xgr\\t%0,%2
xr\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -4959,8 +5009,7 @@
"@
xgr\\t%0,%2
xg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
@@ -4969,8 +5018,7 @@
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*xordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
@@ -4979,8 +5027,7 @@
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; xorsi3 instruction pattern(s).
@@ -4988,42 +5035,42 @@
(define_insn "*xorsi3_cc"
[(set (reg 33)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
- x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ x\\t%0,%2
+ xy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
- x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ x\\t%0,%2
+ xy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SI 2 "general_operand" "d,m")))
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))]
""
"@
xr\\t%0,%2
- x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ x\\t%0,%2
+ xy\\t%0,%2"
+ [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
@@ -5032,8 +5079,7 @@
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*xorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
@@ -5042,8 +5088,7 @@
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; xorhi3 instruction pattern(s).
@@ -5056,8 +5101,7 @@
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*xorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
@@ -5066,8 +5110,7 @@
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*xorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
@@ -5076,8 +5119,7 @@
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; xorqi3 instruction pattern(s).
@@ -5090,32 +5132,31 @@
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(xor:QI (match_dup 0)
- (match_operand:QI 1 "s_imm_operand" "n,Q")))
+ (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
+ xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*xorqi3_ss_inv"
- [(set (match_operand:QI 0 "s_operand" "=Q,Q")
- (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
+ [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
+ (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0)))
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
+ xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SIY,SS")])
;;
@@ -5193,7 +5234,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
(define_insn "*negdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -5201,7 +5243,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimpd")])
;
; negsf2 instruction pattern(s).
@@ -5221,7 +5264,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -5229,7 +5273,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimps")])
;;
@@ -5278,7 +5323,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
(define_insn "*absdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
@@ -5286,7 +5332,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimpd")])
;
; abssf2 instruction pattern(s).
@@ -5306,7 +5353,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
(define_insn "*abssf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -5314,7 +5362,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimps")])
;;
;;- Square root instructions.
@@ -5326,12 +5375,12 @@
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
+ (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
- [(set_attr "op_type" "RRE,RSE")])
+ [(set_attr "op_type" "RRE,RXE")])
;
; sqrtsf2 instruction pattern(s).
@@ -5339,12 +5388,12 @@
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
+ (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
- [(set_attr "op_type" "RRE,RSE")])
+ [(set_attr "op_type" "RRE,RXE")])
;;
;;- One complement instructions.
@@ -5419,7 +5468,8 @@
"@
rllg\\t%0,%1,%c2
rllg\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
;
; rotlsi3 instruction pattern(s).
@@ -5433,7 +5483,8 @@
"@
rll\\t%0,%1,%c2
rll\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
;;
@@ -5459,7 +5510,8 @@
"@
sldl\\t%0,%c2
sldl\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "*ashldi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -5469,7 +5521,8 @@
"@
sllg\\t%0,%1,%2
sllg\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
;
; ashrdi3 instruction pattern(s).
@@ -5495,7 +5548,8 @@
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
[(set (reg 33)
@@ -5507,7 +5561,8 @@
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -5518,8 +5573,9 @@
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
-
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
+
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
@@ -5531,7 +5587,8 @@
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
[(set (reg 33)
@@ -5543,7 +5600,8 @@
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -5554,7 +5612,9 @@
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
+
;
; ashlsi3 instruction pattern(s).
@@ -5568,7 +5628,8 @@
"@
sll\\t%0,%c2
sll\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
;
; ashrsi3 instruction pattern(s).
@@ -5585,7 +5646,9 @@
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
+
(define_insn "*ashrsi3_cconly"
[(set (reg 33)
@@ -5597,7 +5660,8 @@
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -5608,7 +5672,8 @@
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
;;
@@ -5634,7 +5699,8 @@
"@
srdl\\t%0,%c2
srdl\\t%0,0(%2)"
- [(set_attr "op_type" "RS,RS")])
+ [(set_attr "op_type" "RS,RS")
+ (set_attr "atype" "reg")])
(define_insn "*lshrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -5644,7 +5710,8 @@
"@
srlg\\t%0,%1,%c2
srlg\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE,RSE")])
+ [(set_attr "op_type" "RSE,RSE")
+ (set_attr "atype" "reg")])
;
; lshrsi3 instruction pattern(s).
@@ -5658,7 +5725,8 @@
"@
srl\\t%0,%c2
srl\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
;;
@@ -5849,6 +5917,7 @@
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
@@ -5861,7 +5930,7 @@
[(set (pc)
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (match_operand 0 "address_operand" "p")
+ (match_operand 0 "address_operand" "U")
(pc)))]
""
"*
@@ -5874,7 +5943,8 @@
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
;;
@@ -5898,6 +5968,7 @@
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
@@ -5911,7 +5982,7 @@
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(pc)
- (match_operand 0 "address_operand" "p")))]
+ (match_operand 0 "address_operand" "U")))]
""
"*
{
@@ -5923,7 +5994,8 @@
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
;;
;;- Trap instructions.
@@ -5933,7 +6005,8 @@
[(trap_if (const_int 1) (const_int 0))]
""
"j\\t.+2"
- [(set_attr "op_type" "RX")])
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "branch")])
(define_expand "conditional_trap"
[(set (match_dup 2) (match_dup 3))
@@ -5958,7 +6031,8 @@
(const_int 0))]
""
"j%C0\\t.+2";
- [(set_attr "op_type" "RX")])
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")])
;;
;;- Loop instructions.
@@ -6007,6 +6081,7 @@
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
@@ -6020,7 +6095,7 @@
(if_then_else
(ne (match_operand:SI 1 "register_operand" "d,d")
(const_int 1))
- (match_operand 0 "address_operand" "p,p")
+ (match_operand 0 "address_operand" "U,U")
(pc)))
(set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1)))
@@ -6037,7 +6112,8 @@
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
(define_split
[(set (pc)
@@ -6085,6 +6161,7 @@
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4) (const_int 12)))])
@@ -6094,7 +6171,7 @@
(if_then_else
(ne (match_operand:DI 1 "register_operand" "d,d")
(const_int 1))
- (match_operand 0 "address_operand" "p,p")
+ (match_operand 0 "address_operand" "U,U")
(pc)))
(set (match_operand:DI 2 "register_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1)))
@@ -6111,7 +6188,8 @@
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RRE") (const_string "RXE")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
(define_split
[(set (pc)
@@ -6158,6 +6236,7 @@
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
@@ -6171,7 +6250,7 @@
;
(define_insn "indirect_jump"
- [(set (pc) (match_operand 0 "address_operand" "p"))]
+ [(set (pc) (match_operand 0 "address_operand" "U"))]
""
"*
{
@@ -6183,14 +6262,15 @@
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
;
; casesi instruction pattern(s).
;
(define_insn "casesi_jump"
- [(set (pc) (match_operand 0 "address_operand" "p"))
+ [(set (pc) (match_operand 0 "address_operand" "U"))
(use (label_ref (match_operand 1 "" "")))]
""
"*
@@ -6203,7 +6283,8 @@
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
(define_expand "casesi"
[(match_operand:SI 0 "general_operand" "")
@@ -6382,7 +6463,7 @@
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "basr_31"
[(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
@@ -6392,27 +6473,25 @@
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "bas_64"
- [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
+ [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
(define_insn "bas_31"
- [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
+ [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
;
@@ -6507,7 +6586,8 @@
"TARGET_64BIT"
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")])
(define_insn "basr_r_31"
[(set (match_operand 0 "register_operand" "=df")
@@ -6518,29 +6598,28 @@
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
+
;;
;;- Thread-local storage support.
@@ -6554,7 +6633,7 @@
ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
stam\\t%%a0,%%a1,%0"
[(set_attr "op_type" "NN,RS")
- (set_attr "atype" "reg,mem")
+ (set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
(set_attr "length" "14,*")])
@@ -6565,8 +6644,7 @@
"@
ear\\t%0,%%a0
stam\\t%%a0,%%a0,%0"
- [(set_attr "op_type" "RRE,RS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RS")])
(define_insn "set_tp_64"
[(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP)
@@ -6576,7 +6654,7 @@
sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
lam\\t%%a0,%%a1,%0"
[(set_attr "op_type" "NN,RS")
- (set_attr "atype" "reg,mem")
+ (set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
(set_attr "length" "14,*")])
@@ -6586,8 +6664,7 @@
"@
sar\\t%%a0,%0
lam\\t%%a0,%%a0,%0"
- [(set_attr "op_type" "RRE,RS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RS")])
(define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d")
@@ -6596,18 +6673,18 @@
UNSPEC_TLS_LOAD))]
"TARGET_64BIT"
"lg\\t%0,%1%J2"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
(define_insn "*tls_load_31"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
(match_operand:SI 2 "" "")]
UNSPEC_TLS_LOAD))]
"!TARGET_64BIT"
- "l\\t%0,%1%J2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ "@
+ l\\t%0,%1%J2
+ ly\\t%0,%1%J2"
+ [(set_attr "op_type" "RX,RXY")])
(define_expand "call_value_tls"
[(set (match_operand 0 "" "")
@@ -6703,11 +6780,11 @@
"basr\\t%3,%1%J4"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "bas_tls_64"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
@@ -6715,11 +6792,11 @@
"bas\\t%3,%a1%J4"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "bas_tls_31"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
+ (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]
@@ -6727,7 +6804,7 @@
"bas\\t%3,%a1%J4"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
;;
;;- Miscellaneous instructions.
@@ -7030,7 +7107,7 @@
"TARGET_64BIT"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "la")])
+ (set_attr "type" "larl")])
(define_insn "reload_anchor"
[(set (match_operand:SI 0 "register_operand" "=a")
@@ -7039,6 +7116,7 @@
"l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
[(set_attr "op_type" "NN")
(set_attr "type" "la")
+ (set_attr "atype" "agen")
(set_attr "length" "8")])
(define_insn "pool"
@@ -7079,7 +7157,7 @@
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "*return_di"
[(return)
@@ -7088,7 +7166,7 @@
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "literal_pool_31"
[(unspec_volatile [(const_int 0)] 300)
@@ -7112,7 +7190,7 @@
return "";
}
[(set_attr "op_type" "NN")
- (set_attr "type" "la")])
+ (set_attr "type" "larl")])
(define_insn "literal_pool_64"
[(unspec_volatile [(const_int 0)] 300)
@@ -7130,4 +7208,4 @@
return "";
}
[(set_attr "op_type" "NN")
- (set_attr "type" "la")])
+ (set_attr "type" "larl")])
--- gcc-3.3.4/gcc/config.gcc.orig 2004-04-29 00:42:47.000000000 -0400
+++ gcc-3.3.4/gcc/config.gcc 2004-06-23 14:31:37.000000000 -0400
@@ -2995,6 +2995,29 @@
cxx_target_objs="${cxx_target_objs} rs6000-c.o"
tmake_file="${tmake_file} rs6000/t-rs6000-c-rule"
;;
+s390*-*-*)
+ case "x$with_cpu" in
+ x)
+ ;;
+
+ xg5 | xg6 | xz900 | xz990)
+ target_cpu_default2="\\\"$with_cpu\\\""
+ ;;
+
+ xyes | xno)
+ echo "--with-cpu must be passed a value" 1>&2
+ exit 1
+ ;;
+
+ *)
+ if test x$pass2done = xyes
+ then
+ echo "Unknown cpu used with --with-cpu=$with_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ esac
+ ;;
sparc*-*-*)
case ".$with_cpu" in
.)
--- gcc-3.3.4/gcc/doc/invoke.texi.orig 2004-03-26 12:28:27.000000000 -0500
+++ gcc-3.3.4/gcc/doc/invoke.texi 2004-06-23 14:31:37.000000000 -0400
@@ -593,9 +593,10 @@
-masm-optimize -mbranch-cost=@var{n} -mcond-exec=@var{n}}
@emph{S/390 and zSeries Options}
-@gccoptlist{-mhard-float -msoft-float -mbackchain -mno-backchain @gol
+@gccoptlist{-march=@var{cpu-type} -mtune=@var{cpu-type} @gol
+-mhard-float -msoft-float -mbackchain -mno-backchain @gol
-msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol
--m64 -m31 -mdebug -mno-debug}
+-m64 -m31 -mesa -mzarch -mdebug -mno-debug}
@emph{CRIS Options}
@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol
@@ -9770,6 +9771,19 @@
targets, the default is @option{-m31}, while the @samp{s390x}
targets default to @option{-m64}.
+@item -mzarch
+@itemx -mesa
+@opindex mzarch
+@opindex mesa
+When @option{-mzarch} is specified, generate code using the
+instructions available on z/Architecture.
+When @option{-mesa} is specified, generate code using the
+instructions available on ESA/390. Note that @option{-mesa} is
+not possible with @option{-m64}.
+When generating code compliant to the Linux for S/390 ABI,
+the default is @option{-mesa}. When generating code compliant
+to the Linux for zSeries ABI, the default is @option{-mzarch}.
+
@item -mmvcle
@itemx -mno-mvcle
@opindex mmvcle
@@ -9785,6 +9799,22 @@
Print (or do not print) additional debug information when compiling.
The default is to not print debug information.
+@item -march=@var{cpu-type}
+@opindex march
+Generate code that will run on @var{cpu-type}, which is the name of a system
+representing a certain processor type. Possible values for
+@var{cpu-type} are @samp{g5}, @samp{g6}, @samp{z900}, and @samp{z990}.
+When generating code using the instructions available on z/Architecture,
+the default is @option{-march=z900}. Otherwise, the default is
+@option{-march=g5}.
+
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Tune to @var{cpu-type} everything applicable about the generated code,
+except for the ABI and the set of available instructions.
+The list of @var{cpu-type} values is the same as for @option{-march}.
+The default is the value used for @option{-march}.
+
@end table
@node CRIS Options
--- gcc-3.3.4/gcc/loop.c.orig 2004-05-29 19:27:30.000000000 -0400
+++ gcc-3.3.4/gcc/loop.c 2004-06-23 14:31:37.000000000 -0400
@@ -299,8 +299,8 @@
rtx, rtx, rtx, rtx, rtx, rtx, int,
enum g_types, int, int, rtx *));
static void update_giv_derive PARAMS ((const struct loop *, rtx));
-static void check_ext_dependent_givs PARAMS ((struct iv_class *,
- struct loop_info *));
+static void check_ext_dependent_givs PARAMS ((const struct loop *,
+ struct iv_class *));
static int basic_induction_var PARAMS ((const struct loop *, rtx,
enum machine_mode, rtx, rtx,
rtx *, rtx *, rtx **));
@@ -5181,7 +5181,7 @@
/* Check each extension dependent giv in this class to see if its
root biv is safe from wrapping in the interior mode. */
- check_ext_dependent_givs (bl, loop_info);
+ check_ext_dependent_givs (loop, bl);
/* Combine all giv's for this iv_class. */
combine_givs (regs, bl);
@@ -7440,10 +7440,11 @@
make the giv illegal. */
static void
-check_ext_dependent_givs (bl, loop_info)
+check_ext_dependent_givs (loop, bl)
+ const struct loop *loop;
struct iv_class *bl;
- struct loop_info *loop_info;
{
+ struct loop_info *loop_info = LOOP_INFO (loop);
int ze_ok = 0, se_ok = 0, info_ok = 0;
enum machine_mode biv_mode = GET_MODE (bl->biv->src_reg);
HOST_WIDE_INT start_val;
@@ -7454,9 +7455,6 @@
/* Make sure the iteration data is available. We must have
constants in order to be certain of no overflow. */
- /* ??? An unknown iteration count with an increment of +-1
- combined with friendly exit tests of against an invariant
- value is also ameanable to optimization. Not implemented. */
if (loop_info->n_iterations > 0
&& bl->initial_value
&& GET_CODE (bl->initial_value) == CONST_INT
@@ -7523,6 +7521,37 @@
}
}
+ /* If we know the BIV is compared at run-time against an
+ invariant value, and the increment is +/- 1, we may also
+ be able to prove that the BIV cannot overflow. */
+ else if (bl->biv->src_reg == loop_info->iteration_var
+ && loop_info->comparison_value
+ && loop_invariant_p (loop, loop_info->comparison_value)
+ && (incr = biv_total_increment (bl))
+ && GET_CODE (incr) == CONST_INT)
+ {
+ /* If the increment is +1, and the exit test is a <,
+ the BIV cannot overflow. (For <=, we have the
+ problematic case that the comparison value might
+ be the maximum value of the range.) */
+ if (INTVAL (incr) == 1)
+ {
+ if (loop_info->comparison_code == LT)
+ se_ok = ze_ok = 1;
+ else if (loop_info->comparison_code == LTU)
+ ze_ok = 1;
+ }
+
+ /* Likewise for increment -1 and exit test >. */
+ if (INTVAL (incr) == -1)
+ {
+ if (loop_info->comparison_code == GT)
+ se_ok = ze_ok = 1;
+ else if (loop_info->comparison_code == GTU)
+ ze_ok = 1;
+ }
+ }
+
/* Invalidate givs that fail the tests. */
for (v = bl->giv; v; v = v->next_iv)
if (v->ext_dependent)
@@ -7544,8 +7573,9 @@
signed or unsigned, so to safely truncate we must satisfy
both. The initial check here verifies the BIV itself;
once that is successful we may check its range wrt the
- derived GIV. */
- if (se_ok && ze_ok)
+ derived GIV. This works only if we were able to determine
+ constant start and end values above. */
+ if (se_ok && ze_ok && info_ok)
{
enum machine_mode outer_mode = GET_MODE (v->ext_dependent);
unsigned HOST_WIDE_INT max = GET_MODE_MASK (outer_mode) >> 1;
