/* NDS32-specific support for 32-bit ELF.
Copyright (C) 2012-2024 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef NDS32_ASM_H
#define NDS32_ASM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Constant values for assembler. */
enum
{
/* Error code for assembling an instruction. */
NASM_OK = 0,
NASM_ERR_UNKNOWN_OP,
NASM_ERR_SYNTAX,
NASM_ERR_OPERAND,
NASM_ERR_OUT_OF_RANGE,
NASM_ERR_REG_REDUCED,
NASM_ERR_JUNK_EOL,
/* Results of parse_operand. */
NASM_R_CONST,
NASM_R_SYMBOL,
NASM_R_ILLEGAL,
/* Attributes for registers. */
NASM_ATTR_RDREG = 0x000100
};
/* We only support one core for now. */
#define NDS32_CORE_COUNT 1
#define NDS32_MAIN_CORE 0
enum
{
/* This operand is used for input or output. (define or use) */
SYN_INPUT = 0x10000,
SYN_OUTPUT = 0x20000,
SYN_LOPT = 0x40000,
SYN_ROPT = 0x80000,
/* Hardware resources:
Current set up allows up to 256 resources for each class
defined above. */
HW_GPR = NDS32_MAIN_CORE << 8,
HW_USR,
HW_DXR,
HW_SR,
HW_FSR,
HW_FDR,
HW_CP, /* Co-processor ID. */
HW_CPR, /* Co-processor registers. */
HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */
HW_ABM, /* [ab]m? flag for LSMWZB. */
HW_DTITON,
HW_DTITOFF,
HW_DPREF_ST,
HW_CCTL_ST0,
HW_CCTL_ST1,
HW_CCTL_ST2,
HW_CCTL_ST3,
HW_CCTL_ST4,
HW_CCTL_ST5,
HW_CCTL_LV,
HW_TLBOP_ST,
HW_STANDBY_ST,
HW_MSYNC_ST,
HW_AEXT_IM_I,
HW_AEXT_IM_M,
HW_AEXT_ACC,
HW_AEXT_ARIDX,
HW_AEXT_ARIDX2,
HW_AEXT_ARIDXI,
HW_AEXT_ARIDXI_MX,
_HW_LAST,
HW_INT = 0x1000,
HW_UINT
};
typedef struct nds32_opcode
{
/* Opcode for the instruction. */
const char *opcode;
/* Human readable string of this instruction. */
const char *instruction;
/* Base value of this instruction. */
uint32_t value;
/* The byte-size of the instruction. */
int isize;
/* Attributes of this instruction. */
uint64_t attr;
/* Implicit define/use. */
uint64_t defuse;
/* Parsed string for assembling. */
lex_t *syntax;
/* Number of variant. */
int variant;
/* Next form of the same mnemonic. */
struct nds32_opcode *next;
/* TODO: Extra constrains and verification.
For example, `mov55 $sp, $sp' is not allowed in v3. */
} opcode_t;
typedef struct nds32_asm_insn
{
/* Assembled instruction bytes. */
uint32_t insn;
/* The opcode structure for this instruction. */
struct nds32_opcode *opcode;
/* The field need special fix-up, used for relocation. */
const struct nds32_field *field;
/* Attributes for relocation. */
uint64_t attr;
/* Application-dependent data, e.g., expression. */
void *info;
/* Input/output registers. */
uint64_t defuse;
} nds32_asm_insn_t;
typedef struct nds32_asm_desc
{
/* The callback provided by assembler user for parse an operand,
e.g., parse integer. */
int (*parse_operand) (struct nds32_asm_desc *,
struct nds32_asm_insn *,
char **, int64_t *);
/* Result of assembling. */
int result;
/* The mach for this assembling. */
int mach;
int flags;
} nds32_asm_desc_t;
/* The field information for an operand. */
typedef struct nds32_field
{
/* Name of the field. */
const char *name;
