/* cr16.h -- Header file for CR16 opcode and register tables.
Copyright (C) 2007-2024 Free Software Foundation, Inc.
Contributed by M R Swami Reddy
This file is part of GAS, GDB and the GNU binutils.
GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3, or (at your
option) any later version.
GAS, GDB, and GNU binutils are distributed in the hope that they will be
useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _CR16_H_
#define _CR16_H_
/* CR16 core Registers :
The enums are used as indices to CR16 registers table (cr16_regtab).
Therefore, order MUST be preserved. */
/* Not a register. */
nullregister,
MAX_REG
}
reg;
/* CR16 processor registers and special registers :
The enums are used as indices to CR16 processor registers table
(cr16_pregtab). Therefore, order MUST be preserved. */
/* CR16 argument types :
The argument types correspond to instructions operands
Argument types :
r - register
rp - register pair
c - constant
i - immediate
idxr - index with register
idxrp - index with register pair
rbase - register base
rpbase - register pair base
pr - processor register. */
/* Maximum value supported for instruction types. */
#define CR16_INS_MAX (1 << 4)
/* Mask to record an instruction type. */
#define CR16_INS_MASK (CR16_INS_MAX - 1)
/* Return instruction type, given instruction's attributes. */
#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK)
/* Indicates whether this instruction has a register list as parameter. */
#define REG_LIST CR16_INS_MAX
/* The operands in binary and assembly are placed in reverse order.
load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
#define REVERSE_MATCH (1 << 5)
/* Instruction shouldn't allow to push a register which is used as a rptr. */
#define NO_RPTR (1 << 18)
/* Maximum operands per instruction. */
#define MAX_OPERANDS 5
/* Maximum register name length. */
#define MAX_REGNAME_LEN 10
/* Maximum instruction length. */
#define MAX_INST_LEN 256
/* Values defined for the flags field of a struct operand_entry. */
/* Operand must be an unsigned number. */
#define OP_UNSIGNED (1 << 0)
/* Operand must be a signed number. */
#define OP_SIGNED (1 << 1)
/* Operand must be a negative number. */
#define OP_NEG (1 << 2)
/* A special load/stor 4-bit unsigned displacement operand. */
#define OP_DEC (1 << 3)
/* Operand must be an even number. */
#define OP_EVEN (1 << 4)
/* Operand is shifted right. */
#define OP_SHIFT (1 << 5)
/* Operand is shifted right and decremented. */
#define OP_SHIFT_DEC (1 << 6)
/* Operand has reserved escape sequences. */
#define OP_ESC (1 << 7)
/* Operand must be a ABS20 number. */
#define OP_ABS20 (1 << 8)
/* Operand must be a ABS24 number. */
#define OP_ABS24 (1 << 9)
/* Operand has reserved escape sequences type 1. */
#define OP_ESC1 (1 << 10)
/* Single operand description. */
typedef struct
{
/* Operand type. */
operand_type op_type;
/* Operand location within the opcode. */
unsigned int shift;
}
operand_desc;
/* Instruction data structure used in instruction table. */
typedef struct
{
/* Name. */
const char *mnemonic;
/* Size (in words). */
unsigned int size;
/* Constant prefix (matched by the disassembler). */
unsigned long match; /* ie opcode */
/* Match size (in bits). */
/* MASK: if( (i & match_bits) == match ) then match */
int match_bits;
/* Attributes. */
unsigned int flags;
/* Operands (always last, so unreferenced operands are initialized). */
operand_desc operands[MAX_OPERANDS];
}
inst;
/* Data structure for a single instruction's arguments (Operands). */
typedef struct
{
/* Register or base register. */
reg r;
/* Register pair register. */
reg rp;
/* Index register. */
reg i_r;
/* Processor register. */
preg pr;
/* Processor register. 32 bit */
preg prp;
/* Constant/immediate/absolute value. */
long constant;
/* CC code. */
unsigned int cc;
/* Scaled index mode. */
unsigned int scale;
/* Argument type. */
argtype type;
/* Size of the argument (in bits) required to represent. */
int size;
/* The type of the expression. */
unsigned char X_op;
}
argument;
/* Internal structure to hold the various entities
corresponding to the current assembling instruction. */
typedef struct
{
/* Number of arguments. */
int nargs;
/* The argument data structure for storing args (operands). */
argument arg[MAX_OPERANDS];
/* The following fields are required only by CR16-assembler. */
#ifdef TC_CR16
/* Expression used for setting the fixups (if any). */
expressionS exp;
bfd_reloc_code_real_type rtype;
#endif /* TC_CR16 */
/* Instruction size (in bytes). */
int size;
}
ins;
/* Structure to hold information about predefined operands. */
typedef struct
{
/* Size (in bits). */
unsigned int bit_size;
/* Argument type. */
argtype arg_type;
/* One bit syntax flags. */
int flags;
}
operand_entry;
/* Structure to hold trap handler information. */
typedef struct
{
/* Trap name. */
char *name;
/* Index in dispatch table. */
unsigned int entry;
}
trap_entry;
/* Structure to hold information about predefined registers. */
/* CR16 CC - codes bit table. */
extern const char * cr16_b_cond_tab[];
extern const unsigned int cr16_num_cc;
#define NUMCC cr16_num_cc;
/* Table of instructions with no operands. */
extern const char * cr16_no_op_insn[];
/* A macro for representing the instruction "constant" opcode, that is,
the FIXED part of the instruction. The "constant" opcode is represented
as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
over that range. */
#define BIN(OPC,SHIFT) (OPC << SHIFT)
/* Is the current instruction type is TYPE ? */
#define IS_INSN_TYPE(TYPE) \
(CR16_INS_TYPE (instruction->flags) == TYPE)
/* Is the current instruction mnemonic is MNEMONIC ? */
#define IS_INSN_MNEMONIC(MNEMONIC) \
(strcmp (instruction->mnemonic, MNEMONIC) == 0)
/* Does the current instruction has register list ? */
#define INST_HAS_REG_LIST \
(instruction->flags & REG_LIST)
/* Utility macros for string comparison. */
#define streq(a, b) (strcmp (a, b) == 0)
/* Long long type handling. */
/* Replace all appearances of 'long long int' with LONGLONG. */
typedef long long int LONGLONG;
typedef unsigned long long ULONGLONG;
/* Data types for opcode handling. */
typedef unsigned long dwordU;
typedef unsigned short wordU;
/* Prototypes for function in cr16-dis.c. */
extern void cr16_make_instruction (void);
extern int cr16_match_opcode (void);
